Diode Tested Devices

DOD400 DU3CD1 DU3CD2 DU3CD3 DU3ED1 DU3ED2 DAD1 DAD2 DAULED1 DAULED2
DAULED3 DAULED4 DAULED5 DAULED6 DGD15 DGD16 DGD4 DPD101 DPD102 DPD103
DPD201 DPD202 DPD501 DPD601 DPD701 DSD1 DSD2 DSD5 DUD21 DUD22
DUD31 DUD32 DUD33 DUD34 DUD4 DUD5 DUD6      

DOD400
Device Loc Side Total Pin Tested Coverage (%) Comment
DOD400 F1 T 6 6 100.0 No Test Nail

Pin Nail Net Name
1 1710 O_KB_DATA_R
2 1 GND
3 1707 O_KB_CLK_R
4 0 NC_2122
5 0 NC_2123
6 0 NC_2124

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2679 DOD400_1_2 0.700V 0.850V 1 D 1 1710 0 1.105V 0.595V 0.870V 0.0000 15710207 14698388 1.1100 0.6000  
2680 DOD400_2_3 0.700V 0.850V 1 D 1 1707 0 1.105V 0.595V 0.860V 0.0000 6443566 6065455 1.1100 0.6000  
2681 DOD400/NP_3_ 0.700V 0.700V 0 D 0 1707 0 0.910V 0.490V NA NA NA NA NA NA  
2682 DOD400/NP_4_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2683 DOD400/NP_5_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2684 DOD400/NP_6_ 0.700V 0.700V 0 D 1710 0 0 0.910V 0.490V NA NA NA NA NA NA  

DU3CD1
Device Loc Side Total Pin Tested Coverage (%) Comment
DU3CD1 D1 T 6 6 100.0 No Test Nail

Pin Nail Net Name
1 0 NC_2119
2 1 GND
3 764 U3C1_DFP_CC1
4 766 U3C1_DFP_CC2
5 0 NC_2120
6 0 NC_2121

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2729 DU3CD1/NP_1_ 0.700V 0.700V 0 D 0 1 0 0.910V 0.490V NA NA NA NA NA NA  
2730 DU3CD1/NP_4_ 0.700V 0.700V 0 D 766 0 0 0.910V 0.490V NA NA NA NA NA NA  
2731 DU3CD1/NP_5_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2732 DU3CD1/NP_6_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2733 DU3CD1_2_3 0.700V 0.850V 1 D 1 764 0 1.105V 0.595V 0.880V 0.0008 100.85 89.542 1.1100 0.6000  
2734 DU3CD1_3_4 0.700V 0.850V 1 D 1 766 0 1.105V 0.595V 0.880V 0.0008 100.85 90.120 1.1100 0.6000  

DU3CD2
Device Loc Side Total Pin Tested Coverage (%) Comment
DU3CD2 D1 T 9 9 100.0 No Test Nail

Pin Nail Net Name
1 0 U3C_U3TXDN1
2 0 U3C_U3TXDP1
3 1 GND
4 1277 U3C_U3RXDN1
5 0 U3C_U3RXDP1
6 0 U3C_U3RXDP1
7 1277 U3C_U3RXDN1
8 0 U3C_U3TXDP1
9 0 U3C_U3TXDN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2735 DU3CD2/NP_1_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2736 DU3CD2/NP_2_ 0.700V 0.700V 0 D 0 1 0 0.910V 0.490V NA NA NA NA NA NA  
2737 DU3CD2/NP_4_ 0.700V 0.700V 0 D 1277 0 0 0.910V 0.490V NA NA NA NA NA NA  
2738 DU3CD2/NP_5_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2739 DU3CD2/NP_6_ 0.700V 0.700V 0 D 0 1277 0 0.910V 0.490V NA NA NA NA NA NA  
2740 DU3CD2/NP_7_ 0.700V 0.700V 0 D 1277 0 0 0.910V 0.490V NA NA NA NA NA NA  
2741 DU3CD2/NP_8_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2742 DU3CD2/NP_9_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2743 DU3CD2_3_4 0.700V 0.850V 1 D 1 1277 0 1.105V 0.595V 0.860V 0.0000 9508895 9005348 1.1100 0.6000  

DU3CD3
Device Loc Side Total Pin Tested Coverage (%) Comment
DU3CD3 D1 T 9 9 100.0 No Test Nail

Pin Nail Net Name
1 0 U3C_U3TXDN2
2 1275 U3C_U3TXDP2
3 1 GND
4 0 U3C_U3RXDP2
5 0 U3C_U3RXDN2
6 0 U3C_U3RXDN2
7 0 U3C_U3RXDP2
8 1275 U3C_U3TXDP2
9 0 U3C_U3TXDN2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2744 DU3CD3/NP_1_ 0.700V 0.700V 0 D 0 1275 0 0.910V 0.490V NA NA NA NA NA NA  
2745 DU3CD3/NP_3_ 0.700V 0.700V 0 D 1 0 0 0.910V 0.490V NA NA NA NA NA NA  
2746 DU3CD3/NP_4_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2747 DU3CD3/NP_5_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2748 DU3CD3/NP_6_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2749 DU3CD3/NP_7_ 0.700V 0.700V 0 D 0 1275 0 0.910V 0.490V NA NA NA NA NA NA  
2750 DU3CD3/NP_8_ 0.700V 0.700V 0 D 1275 0 0 0.910V 0.490V NA NA NA NA NA NA  
2751 DU3CD3/NP_9_ 0.700V 0.700V 0 D 0 0 0 0.910V 0.490V NA NA NA NA NA NA  
2752 DU3CD3_2_3 0.757V 0.757V 0 D 1 1275 0 0.984V 0.530V 0.760V 0.0008 89.815 88.878 0.9800 0.5300  

DU3ED1
Device Loc Side Total Pin Tested Coverage (%) Comment
DU3ED1 D1 T 6 6 100.0 No Test Nail

Pin Nail Net Name
1 1261 U3E_U2DP1_R
2 1 GND
3 0 U3C_U2DP2
4 1276 U3C_U2DN2
5 423 +5VSB
6 1260 U3E_U2DN1_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2756 DU3ED1_1_2 0.700V 0.850V 1 D 1 1261 0 1.105V 0.595V 0.860V 0.0008 100.85 98.587 1.1100 0.6000  
2757 DU3ED1/NP_2_ 0.700V 0.850V 1 D 1 0 0 1.105V 0.595V NA NA NA NA NA NA  
2758 DU3ED1/NP_3_ 0.700V 0.850V 1 D 0 1276 0 1.105V 0.595V NA NA NA NA NA NA  
2759 DU3ED1_4_5 0.700V 0.850V 1 D 1276 423 0 1.105V 0.595V 0.900V 0.0000 9508895 7644407 1.1100 0.6000  
2760 DU3ED1_5_6 0.700V 0.850V 1 D 1260 423 0 1.105V 0.595V 0.910V 0.0000 10574033 8137481 1.1100 0.6000  
2761 DU3ED1_6_1 0.700V 0.850V 1 D 1261 423 0 1.105V 0.595V 0.900V 0.0000 9266867 7290679 1.1100 0.6000  

DU3ED2
Device Loc Side Total Pin Tested Coverage (%) Comment
DU3ED2 D1 T 9 9 100.0  

Pin Nail Net Name
1 1263 U3E_U3RXDN1
2 1262 U3E_U3RXDP1
3 1 GND
4 1259 U3E_U3TXDN1
5 1258 U3E_U3TXDP1
6 1258 U3E_U3TXDP1
7 1259 U3E_U3TXDN1
8 1262 U3E_U3RXDP1
9 1263 U3E_U3RXDN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2762 DU3ED2_1_2 0.700V 0.850V 1 D 1 1263 0 1.105V 0.595V 0.870V 0.0000 6904150 6419961 1.1100 0.6000  
2763 DU3ED2_2_3 0.700V 0.850V 1 D 1 1262 0 1.105V 0.595V 0.890V 0.0000 10086562 8455274 1.1100 0.6000  
2764 DU3ED2_3_4 0.700V 0.850V 1 D 1 1259 0 1.105V 0.595V 0.910V 0.0000 10574033 8137481 1.1100 0.6000  
2765 DU3ED2_4_5 0.700V 0.850V 1 D 1 1258 0 1.105V 0.595V 0.910V 0.0000 6938982 5300322 1.1100 0.6000  

DAD1
Device Loc Side Total Pin Tested Coverage (%) Comment
DAD1 A1 T 3 3 100.0  

Pin Nail Net Name
1 27 A_VREF_FMIC1_R
2 26 A_VREF_FMIC1_L
3 23 A_VREF_FMIC1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2584 DAD1_1_2 0.700V 1.500V 0 D 27 26 0 Ignore 1.050V 2.830V 0.0008 177.97 349.54 1.9500 1.0500  
2585 DAD1_2_3 0.417V 0.417V 1 D 23 26 0 0.542V 0.292V 0.420V 0.0008 49.475 49.199 0.5400 0.2900  
2586 DAD1_3_1 0.418V 0.418V 1 D 23 27 0 0.543V 0.293V 0.420V 0.0008 49.594 49.500 0.5400 0.2900  

DAD2
Device Loc Side Total Pin Tested Coverage (%) Comment
DAD2 A1 T 3 3 100.0  

Pin Nail Net Name
1 28 A_VREF_FMIC2_R
2 6 A_VREF_FMIC2_L
3 36 A_VREF_FMIC2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2587 DAD2_1_2 0.700V 1.500V 0 D 28 6 0 Ignore 1.050V 2.830V 0.0008 177.97 349.54 1.9500 1.0500  
2588 DAD2_2_3 0.700V 0.700V 0 D 36 6 0 0.910V 0.490V 2.030V 0.0000 2339688 12526320 0.9100 0.4900  
2589 DAD2_3_1 0.700V 0.700V 0 D 36 28 0 0.910V 0.490V 2.030V 0.0000 2339688 12526320 0.9100 0.4900  

DAULED1
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED1 A1 B 2 2 100.0  

Pin Nail Net Name
1 66 N16978758
2 708 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
4 DAULED1 3.000V 2.000V 1 D 66 708 0 2.600V 1.400V 2.080V 0.0000 14980419 12957516 2.6000 1.4000  

DAULED2
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED2 A1 B 2 2 100.0  

Pin Nail Net Name
1 67 N16978835
2 708 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
5 DAULED2 3.000V 2.000V 1 D 67 708 0 2.600V 1.400V 2.070V 0.0000 5460783 4789810 2.6000 1.4000  

DAULED3
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED3 B1 B 2 2 100.0  

Pin Nail Net Name
1 701 N16978863
2 708 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
6 DAULED3 3.000V 2.000V 1 D 701 708 0 2.600V 1.400V 2.050V 0.0000 13691856 12575853 2.6000 1.4000  

DAULED4
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED4 B1 B 2 2 100.0  

Pin Nail Net Name
1 707 N16978891
2 708 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
7 DAULED4 3.000V 2.000V 1 D 707 708 0 2.600V 1.400V 2.040V 0.0000 14008639 13173574 2.6000 1.4000  

DAULED5
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED5 C1 B 2 2 100.0  

Pin Nail Net Name
1 689 N16978919
2 708 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
8 DAULED5 3.000V 2.000V 1 D 689 708 0 2.600V 1.400V 2.020V 0.0000 15874656 15430474 2.6000 1.4000  

DAULED6
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED6 B1 B 2 2 100.0  

Pin Nail Net Name
1 688 N16978947
2 708 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
9 DAULED6 3.000V 2.000V 1 D 688 708 0 2.600V 1.400V 2.080V 0.0000 14980419 12957516 2.6000 1.4000  

DGD15
Device Loc Side Total Pin Tested Coverage (%) Comment
DGD15 E1 T 6 6 100.0 No Test Nail

Pin Nail Net Name
1 1291 VGA_GREEN_L
2 1 GND
3 1292 VGA_BLUE_L
4 0 NC_2129
5 2 +3V
6 1290 VGA_RED_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2638 DGD15_1_2 0.700V 0.850V 1 D 1 1291 0 1.105V 0.595V 0.820V 0.0008 100.85 87.521 1.1100 0.6000  
2639 DGD15_2_3 0.700V 0.850V 1 D 1 1292 0 1.105V 0.595V 0.820V 0.0008 100.85 88.676 1.1100 0.6000  
2640 DGD15/NP_3_4 0.700V 0.850V 1 D 1292 0 0 1.105V 0.595V NA NA NA NA NA NA  
2641 DGD15/NP_4_5 0.700V 0.850V 1 D 0 2 0 1.105V 0.595V NA NA NA NA NA NA  
2642 DGD15_5_6 0.700V 0.850V 1 D 1290 2 0 1.105V 0.595V 0.880V 0.0008 100.85 89.350 1.1100 0.6000  
2643 DGD15_6_1 0.700V 0.850V 1 D 1291 2 0 1.105V 0.595V 0.890V 0.0000 5378022 4631395 1.1100 0.6000  

DGD16
Device Loc Side Total Pin Tested Coverage (%) Comment
DGD16 F1 T 6 6 100.0  

Pin Nail Net Name
1 1719 VGA_DDC_CLK_R
2 1 GND
3 1288 VGA_DDC_DATA_R
4 1287 VGA_HSYNC_R
5 1705 +V_5V
6 1718 VGA_VSYNC_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2644 DGD16_1_2 0.700V 0.850V 1 D 1 1719 0 1.105V 0.595V 0.870V 0.0000 5963195 5408440 1.1100 0.6000  
2645 DGD16_2_3 0.700V 0.850V 1 D 1 1288 0 1.105V 0.595V 0.870V 0.0000 5963195 5408440 1.1100 0.6000  
2646 DGD16_3_4 0.700V 0.850V 1 D 1 1287 0 1.105V 0.595V 0.850V 0.0008 100.85 100.51 1.1100 0.6000  
2647 DGD16_4_5 0.700V 0.850V 1 D 1287 1705 0 1.105V 0.595V 0.900V 0.0000 9701685 7854936 1.1100 0.6000  
2648 DGD16_5_6 0.700V 0.850V 1 D 1718 1705 0 1.105V 0.595V 0.900V 0.0000 9701685 7854936 1.1100 0.6000  
2649 DGD16_6_1 0.700V 0.850V 1 D 1719 1705 0 1.105V 0.595V 0.900V 0.0008 100.85 82.037 1.1100 0.6000  

DGD4
Device Loc Side Total Pin Tested Coverage (%) Comment
DGD4 F1 T 2 2 100.0  

Pin Nail Net Name
1 3 +5V
2 1705 +V_5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2650 DGD4 0.299V 0.299V 1 D 3 1705 0 0.389V 0.209V 0.300V 0.0000 12429312 12365593 0.3900 0.2100  
2651 DGD4 0.700V 1.500V 0 D 1705 3 0 Ignore 1.050V 0.300V 0.0000 12429312 12365593 0.3900 0.2100  

DPD101
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD101 F2 T 3 3 100.0 D

Pin Nail Net Name
1 423 +5VSB
2 1316 +12V_CPU
3 1682 P_DRIVER1_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2685 DPD101_1_2/D 0.700V 1.500V 0 D 423 1316 0 Ignore 1.050V NA NA NA NA NA NA  
2686 DPD101_2_3 0.408V 0.408V 1 D 1316 1682 0 0.530V 0.286V 0.410V 0.0000 9103867 9101695 0.5300 0.2900  
2687 DPD101_3_1 0.412V 0.412V 1 D 423 1682 0 0.536V 0.288V 0.400V 0.0000 6106355 5333198 0.5400 0.2900  

DPD102
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD102 F2 T 3 3 100.0 D

Pin Nail Net Name
1 423 +5VSB
2 1316 +12V_CPU
3 1686 P_DRIVER2_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2688 DPD102_1_2/D 0.700V 1.500V 0 D 423 1316 0 Ignore 1.050V NA NA NA NA NA NA  
2689 DPD102_2_3 0.407V 0.407V 1 D 1316 1686 0 0.529V 0.285V 0.400V 0.0008 48.289 45.039 0.5300 0.2800  
2690 DPD102_3_1 0.412V 0.412V 1 D 423 1686 0 0.536V 0.288V 0.400V 0.0008 48.882 44.232 0.5400 0.2900  

DPD103
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD103 F2 T 3 3 100.0 D

Pin Nail Net Name
1 423 +5VSB
2 1316 +12V_CPU
3 1687 P_DRIVER3_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2691 DPD103_1_2/D 0.700V 1.500V 0 D 423 1316 0 Ignore 1.050V NA NA NA NA NA NA  
2692 DPD103_2_3 0.408V 0.408V 1 D 1316 1687 0 0.530V 0.286V 0.400V 0.0000 8328000 7634696 0.5300 0.2900  
2693 DPD103_3_1 0.412V 0.412V 1 D 423 1687 0 0.536V 0.288V 0.400V 0.0000 6289724 5716216 0.5400 0.2900  

DPD201
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD201 F3 T 3 3 100.0 D

Pin Nail Net Name
1 423 +5VSB
2 1316 +12V_CPU
3 1651 P_GT_DRIVER_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2694 DPD201_1_2/D 0.700V 1.500V 0 D 423 1316 0 Ignore 1.050V NA NA NA NA NA NA  
2695 DPD201_2_3 0.408V 0.408V 1 D 1316 1651 0 0.530V 0.286V 0.400V 0.0008 48.407 44.762 0.5300 0.2900  
2696 DPD201_3_1 0.414V 0.414V 1 D 423 1651 0 0.538V 0.290V 0.400V 0.0000 38347848 35152080 0.5400 0.2900  

DPD202
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD202 F2 T 3 3 100.0 D

Pin Nail Net Name
1 423 +5VSB
2 1316 +12V_CPU
3 1654 P_GT_DRIVER2_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2697 DPD202_1_2/D 0.700V 1.500V 0 D 423 1316 0 Ignore 1.050V NA NA NA NA NA NA  
2698 DPD202_2_3 0.409V 0.409V 1 D 1316 1654 0 0.532V 0.286V 0.400V 0.0000 9858511 9076745 0.5300 0.2900  
2699 DPD202_3_1 0.414V 0.414V 1 D 423 1654 0 0.538V 0.290V 0.400V 0.0008 49.119 44.833 0.5400 0.2900  

DPD501
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD501 F4 T 3 3 100.0 D

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 4 +12V
3 1498 P_VDDQ_VCC_P_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2700 DPD501_1_2/D 0.700V 1.500V 0 D 1229 4 0 Ignore 1.050V NA NA NA NA NA NA  
2701 DPD501_2_3 0.412V 0.412V 1 D 4 1498 0 0.536V 0.288V 0.400V 0.0025 16.294 14.616 0.5400 0.2900  
2702 DPD501_3_1 0.414V 0.414V 1 D 1229 1498 0 0.538V 0.290V 0.370V 0.0042 9.8240 6.7340 0.5400 0.2900  

DPD601
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD601 B4 T 3 3 100.0 No Test Nail

Pin Nail Net Name
1 0 NC_2184
2 413 P_5VSB_GATE_D_10
3 412 P_5VSB_GATE_10_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2703 DPD601/NP_1_ 0.700V 0.700V 0 D 0 413 0 0.910V 0.490V NA NA NA NA NA NA  
2704 DPD601/NP_3_ 0.700V 0.700V 0 D 0 412 0 0.910V 0.490V NA NA NA NA NA NA  
2705 DPD601_2_3 0.325V 0.325V 0 D 412 413 0 0.422V 0.227V 0.330V 0.0000 6348117 6264948 0.4200 0.2300  

DPD701
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD701 B4 T 3 3 100.0  

Pin Nail Net Name
1 427 N21292828
2 424 P_+1_0V_A_PG_10
3 198 O_RSMRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2706 DPD701_1_2 0.700V 1.500V 0 D 427 424 0 Ignore 1.050V 2.840V 0.0000 3568581 7047442 1.9500 1.0500  
2707 DPD701_2_3 0.453V 0.453V 1 D 198 424 0 0.589V 0.317V 0.450V 0.0000 9207619 9188332 0.5900 0.3200  
2708 DPD701_3_1 0.452V 0.452V 1 D 198 427 0 0.588V 0.316V 0.450V 0.0008 53.628 53.312 0.5900 0.3200  

DSD1
Device Loc Side Total Pin Tested Coverage (%) Comment
DSD1 B3 T 3 3 100.0  

Pin Nail Net Name
1 546 N31918039
2 554 +BAT_R
3 678 +3V_BAT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2709 DSD1_1_2 0.700V 1.500V 0 D 546 554 0 Ignore 1.050V 2.840V 0.0008 177.97 350.69 1.9500 1.0500  
2710 DSD1_2_3 0.417V 0.417V 1 D 554 678 0 0.542V 0.292V 0.420V 0.0008 49.475 48.597 0.5400 0.2900  
2711 DSD1_3_1 0.414V 0.414V 1 D 546 678 0 0.538V 0.290V 0.420V 0.0000 6405807 6337290 0.5400 0.2900  

DSD2
Device Loc Side Total Pin Tested Coverage (%) Comment
DSD2 D2 T 3 3 100.0  

Pin Nail Net Name
1 1194 N45021399
2 1171 H_THERMTRIP_
3 817 S_VCORE_SHDN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2712 DSD2_1_2 0.700V 1.500V 0 D 1194 1171 0 Ignore 1.050V 2.820V 0.0000 4286213 8325613 1.9500 1.0500  
2713 DSD2_2_3 0.415V 0.415V 1 D 817 1171 0 0.539V 0.290V 0.420V 0.0000 10172759 10026637 0.5400 0.2900  
2714 DSD2_3_1 0.415V 0.415V 1 D 817 1194 0 0.539V 0.290V 0.420V 0.0008 49.238 48.723 0.5400 0.2900  

DSD5
Device Loc Side Total Pin Tested Coverage (%) Comment
DSD5 A4 T 3 3 100.0 No Test Nail

Pin Nail Net Name
1 1518 S_SLP_S3_
2 0 NC_2185
3 372 S_SYSPWROK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2718 DSD5/NP_1_2 0.700V 0.700V 0 D 1518 0 0 0.910V 0.490V NA NA NA NA NA NA  
2719 DSD5/NP_2_3 0.700V 0.700V 0 D 0 372 0 0.910V 0.490V NA NA NA NA NA NA  
2720 DSD5_3_1 0.447V 0.447V 1 D 372 1518 0 0.581V 0.313V 0.450V 0.0000 8304118 8276545 0.5800 0.3100  

DUD21
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD21 C4 T 6 6 100.0  

Pin Nail Net Name
1 955 S_U2DP1
2 1 GND
3 953 S_U2DP2
4 954 S_U2DN2
5 423 +5VSB
6 956 S_U2DN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2775 DUD21_1_2 0.700V 0.850V 1 D 1 955 0 1.105V 0.595V 0.860V 0.0000 5601270 5464987 1.1100 0.6000  
2776 DUD21_2_3 0.700V 0.850V 1 D 1 953 0 1.105V 0.595V 0.860V 0.0000 18777290 18212924 1.1100 0.6000  
2777 DUD21_3_4 0.700V 0.850V 1 D 1 954 0 1.105V 0.595V 0.860V 0.0000 7521269 7252153 1.1100 0.6000  
2778 DUD21_4_5 0.700V 0.850V 1 D 954 423 0 1.105V 0.595V 0.900V 0.0000 9701685 7854936 1.1100 0.6000  
2779 DUD21_5_6 0.700V 0.850V 1 D 956 423 0 1.105V 0.595V 0.900V 0.0000 9508895 7644407 1.1100 0.6000  
2780 DUD21_6_1 0.700V 0.850V 1 D 955 423 0 1.105V 0.595V 0.900V 0.0000 8777195 7005928 1.1100 0.6000  

DUD22
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD22 D1 T 6 6 100.0  

Pin Nail Net Name
1 1270 S_U2DP4
2 1 GND
3 1267 S_U2DP3
4 1266 S_U2DN3
5 423 +5VSB
6 1271 S_U2DN4

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2781 DUD22_1_2 0.700V 0.850V 1 D 1 1270 0 1.105V 0.595V 0.860V 0.0000 6443566 6065455 1.1100 0.6000  
2782 DUD22_2_3 0.700V 0.850V 1 D 1 1267 0 1.105V 0.595V 0.860V 0.0008 100.85 95.316 1.1100 0.6000  
2783 DUD22_3_4 0.700V 0.850V 1 D 1 1266 0 1.105V 0.595V 0.860V 0.0000 6443566 6065455 1.1100 0.6000  
2784 DUD22_4_5 0.700V 0.850V 1 D 1266 423 0 1.105V 0.595V 0.910V 0.0000 7672565 5992442 1.1100 0.6000  
2785 DUD22_5_6 0.700V 0.850V 1 D 1271 423 0 1.105V 0.595V 0.910V 0.0000 7672565 5992442 1.1100 0.6000  
2786 DUD22_6_1 0.700V 0.850V 1 D 1270 423 0 1.105V 0.595V 0.910V 0.0008 100.85 77.803 1.1100 0.6000  

DUD31
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD31 C4 T 9 9 100.0  

Pin Nail Net Name
1 964 S_U3RXDN1
2 963 S_U3RXDP1
3 1 GND
4 962 S_U3RXDN2
5 961 S_U3RXDP2
6 961 S_U3RXDP2
7 962 S_U3RXDN2
8 963 S_U3RXDP1
9 964 S_U3RXDN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2799 DUD31_1_2 0.700V 0.850V 1 D 1 964 0 1.105V 0.595V 0.860V 0.0000 9508895 9005348 1.1100 0.6000  
2800 DUD31_2_3 0.700V 0.850V 1 D 1 963 0 1.105V 0.595V 0.870V 0.0000 15710207 14698388 1.1100 0.6000  
2801 DUD31_3_4 0.700V 0.850V 1 D 1 962 0 1.105V 0.595V 0.860V 0.0000 6443566 6065455 1.1100 0.6000  
2802 DUD31_4_5 0.700V 0.850V 1 D 1 961 0 1.105V 0.595V 0.860V 0.0008 100.85 95.316 1.1100 0.6000  

DUD32
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD32 C4 T 9 9 100.0  

Pin Nail Net Name
1 960 S_U3TXDN1
2 959 S_U3TXDP1
3 1 GND
4 958 S_U3TXDN2
5 957 S_U3TXDP2
6 957 S_U3TXDP2
7 958 S_U3TXDN2
8 959 S_U3TXDP1
9 960 S_U3TXDN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2803 DUD32_1_2 0.700V 0.850V 1 D 1 960 0 1.105V 0.595V 0.910V 0.0000 7672565 5992442 1.1100 0.6000  
2804 DUD32_2_3 0.700V 0.850V 1 D 1 959 0 1.105V 0.595V 0.910V 0.0008 100.85 78.380 1.1100 0.6000  
2805 DUD32_3_4 0.700V 0.850V 1 D 1 958 0 1.105V 0.595V 0.910V 0.0008 100.85 78.957 1.1100 0.6000  
2806 DUD32_4_5 0.700V 0.850V 1 D 1 957 0 1.105V 0.595V 0.900V 0.0000 9266867 7290679 1.1100 0.6000  

DUD33
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD33 C1 T 9 9 100.0  

Pin Nail Net Name
1 715 S_U3RXDN4
2 1269 S_U3RXDP4
3 1 GND
4 716 S_U3RXDN3
5 1268 S_U3RXDP3
6 1268 S_U3RXDP3
7 716 S_U3RXDN3
8 1269 S_U3RXDP4
9 715 S_U3RXDN4

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2807 DUD33_1_2 0.700V 0.850V 1 D 1 715 0 1.105V 0.595V 0.860V 0.0000 10384117 9893670 1.1100 0.6000  
2808 DUD33_2_3 0.700V 0.850V 1 D 1 1269 0 1.105V 0.595V 0.870V 0.0008 100.85 93.969 1.1100 0.6000  
2809 DUD33_3_4 0.700V 0.850V 1 D 1 716 0 1.105V 0.595V 0.860V 0.0000 9508895 9005348 1.1100 0.6000  
2810 DUD33_4_5 0.700V 0.850V 1 D 1 1268 0 1.105V 0.595V 0.870V 0.0000 15710207 14698388 1.1100 0.6000  

DUD34
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD34 D1 T 9 9 100.0  

Pin Nail Net Name
1 1265 S_U3TXDN3
2 1264 S_U3TXDP3
3 1 GND
4 1272 S_U3TXDN4
5 1273 S_U3TXDP4
6 1273 S_U3TXDP4
7 1272 S_U3TXDN4
8 1264 S_U3TXDP3
9 1265 S_U3TXDN3

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2811 DUD34_1_2 0.700V 0.850V 1 D 1 1265 0 1.105V 0.595V 0.910V 0.0008 100.85 78.573 1.1100 0.6000  
2812 DUD34_2_3 0.700V 0.850V 1 D 1 1264 0 1.105V 0.595V 0.910V 0.0000 10574033 8137481 1.1100 0.6000  
2813 DUD34_3_4 0.700V 0.850V 1 D 1 1272 0 1.105V 0.595V 0.910V 0.0000 9308949 7004029 1.1100 0.6000  
2814 DUD34_4_5 0.700V 0.850V 1 D 1 1273 0 1.105V 0.595V 0.910V 0.0000 8258792 6403017 1.1100 0.6000  

DUD4
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD4 F1 T 6 6 100.0  

Pin Nail Net Name
1 1711 S_USB_PP6
2 1 GND
3 1715 S_USB_PP7
4 1714 S_USB_PN7
5 423 +5VSB
6 1712 S_USB_PN6

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2815 DUD4_1_2 0.700V 0.850V 1 D 1 1711 0 1.105V 0.595V 0.860V 0.0000 18777290 18212924 1.1100 0.6000  
2816 DUD4_2_3 0.700V 0.850V 1 D 1 1715 0 1.105V 0.595V 0.860V 0.0000 7521269 7252153 1.1100 0.6000  
2817 DUD4_3_4 0.700V 0.850V 1 D 1 1714 0 1.105V 0.595V 0.860V 0.0000 28682784 27492288 1.1100 0.6000  
2818 DUD4_4_5 0.700V 0.850V 1 D 1714 423 0 1.105V 0.595V 0.900V 0.0000 129072528 102286344 1.1100 0.6000  
2819 DUD4_5_6 0.700V 0.850V 1 D 1712 423 0 1.105V 0.595V 0.900V 0.0000 129072528 102286344 1.1100 0.6000  
2820 DUD4_6_1 0.700V 0.850V 1 D 1711 423 0 1.105V 0.595V 0.900V 0.0000 129072528 102286344 1.1100 0.6000  

DUD5
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD5 A3 T 6 6 100.0  

Pin Nail Net Name
1 206 S_USB_PP8
2 1 GND
3 205 S_USB_PP9
4 204 S_USB_PN9
5 423 +5VSB
6 202 S_USB_PN8

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2821 DUD5_1_2 0.700V 0.850V 1 D 1 206 0 1.105V 0.595V 0.870V 0.0015 58.225 54.475 1.1100 0.6000  
2822 DUD5_2_3 0.700V 0.850V 1 D 1 205 0 1.105V 0.595V 0.860V 0.0000 28682784 27492288 1.1100 0.6000  
2823 DUD5_3_4 0.700V 0.850V 1 D 1 204 0 1.105V 0.595V 0.860V 0.0000 28682784 27492288 1.1100 0.6000  
2824 DUD5_4_5 0.700V 0.850V 1 D 204 423 0 1.105V 0.595V 0.900V 0.0000 8777195 7005928 1.1100 0.6000  
2825 DUD5_5_6 0.700V 0.850V 1 D 202 423 0 1.105V 0.595V 0.900V 0.0000 8777195 7005928 1.1100 0.6000  
2826 DUD5_6_1 0.700V 0.850V 1 D 206 423 0 1.105V 0.595V 0.900V 0.0000 129072528 102286344 1.1100 0.6000  

DUD6
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD6 A3 T 6 6 100.0  

Pin Nail Net Name
1 190 S_USB_PN10
2 1 GND
3 188 S_USB_PN11
4 189 S_USB_PP11
5 423 +5VSB
6 191 S_USB_PP10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2827 DUD6_1_2 0.700V 0.850V 1 D 1 190 0 1.105V 0.595V 0.860V 0.0000 7521269 7252153 1.1100 0.6000  
2828 DUD6_2_3 0.700V 0.850V 1 D 1 188 0 1.105V 0.595V 0.860V 0.0000 9508895 9005348 1.1100 0.6000  
2829 DUD6_3_4 0.700V 0.850V 1 D 1 189 0 1.105V 0.595V 0.870V 0.0000 7679352 7008907 1.1100 0.6000  
2830 DUD6_4_5 0.700V 0.850V 1 D 189 423 0 1.105V 0.595V 0.910V 0.0000 9308949 7004029 1.1100 0.6000  
2831 DUD6_5_6 0.700V 0.850V 1 D 191 423 0 1.105V 0.595V 0.910V 0.0000 6445574 4886534 1.1100 0.6000  
2832 DUD6_6_1 0.700V 0.850V 1 D 190 423 0 1.105V 0.595V 0.900V 0.0000 8777195 7005928 1.1100 0.6000