Capacitor Tested Devices

CL1C90 CL1C91 CL1C92 CL1C93 CL1U1C22 CD3C365 CD3C38 CD3C40 CD3C46 CD3C47
CD3C48 CPC101 CPC102 CPC103 CPC104 CPC105 CPC106 CPC107 CPC108 CPC109
CPC110 CPC115 CPC116 CPC118 CPC121 CPC122 CPC123 CPC124 CPC126 CPC128
CPC132 CPC133 CPC137 CPC138 CPC140 CPC141 CPC142 CPC143 CPC144 CPC145
CPC193 CPC201 CPC202 CPC203 CPC204 CPC210 CPC412 CPC414 CPC415 CPC418
CPC419 CPC530 CPC531 CPC532 CPC536 CPC537 CPC539 CPC549 CPC552 CPC605
CPC606 CPC607 CPC613 CPC615 CPC616 CPC630 CPC715 CPC731 CPC732 CPC733
CPC736 CPC740 CPC743 CPC751 CPC752 CPC757 CPC759 CPC760 CPC803 CPC804
CPC807 CU3CC194 CU3CCE1 CAC10 CAC11 CAC12 CAC17 CAC18 CAC19 CAC20
CAC21 CAC22 CAC24 CAC27 CAC3 CAC37 CAC38 CAC4 CAC7 CAC8
CAC9 CACE1 CACE10 CACE2 CACE3 CACE4 CACE5 CACE6 CACE7 CACE8
CACE9 CAU1C238 CAU1C27 CAU1C3 CBCN4 CBCN5 CESDATC14 CESDC14 CESDC5 CESDC8
CESDC9 CESDOC205 CGC16 CGC525 CGU1C25 CHC7 CHTC1 CK1PC1 CO1C12 CO1C32
CO1C34 COC2 COC202 COC206 COC3 COC301 COC311 COC321 COC406 COC407
COC760 COC761 COTC1 COU1C31 COU1C45 COU1C53 COU310C1 COU310C4 COU320C1 COU320C4
CPCE100 CPCE108 CPCE207 CPCE514 CPCE518 CPCE707 CSC3 CSC59 CSC60 CSQ40C1
CUCE6 CXCE1                

CL1C90
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1C90 D1 T 2 2 100.0 Parallel JLANU334_26_

Pin Nail Net Name
1 1 GND
2 1244 L1_ACTLEDP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2051 CL1C90/LAN 1000.0pF 1000.0pF 2 C 1 1244 686 1600.0pF 600.0pF 999.7pF 1.6247 102.58 82.009 1600.0 600.00  

CL1C91
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1C91 D1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1245 L1_ACTLEDN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2052 CL1C91 1000.0pF 1000.0pF 2 C 1 1245 0 1600.0pF 600.0pF 1000.8pF 0.7805 213.54 171.17 1600.0 600.00  

CL1C92
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1C92 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 735 L1_LINK1000_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2053 CL1C92 1000.0pF 1000.0pF 2 C 1 735 0 1600.0pF 600.0pF 1002.9pF 0.9012 184.93 149.01 1600.0 600.00  

CL1C93
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1C93 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 736 L1_LINK100_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2054 CL1C93 1000.0pF 1000.0pF 2 C 1 736 0 1600.0pF 600.0pF 1001.0pF 0.4506 369.86 296.67 1600.0 600.00  

CL1U1C22
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1U1C22 B1 T 2 2 100.0 Parallel CL1U1C8

Pin Nail Net Name
1 687 +L1_1_0V
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2362 CL1U1C22/CL1U 1.000uF 1.400uF 0 C 1 687 0 2.240uF 0.840uF 1.150uF 0.0030 76.916 33.864 2.2400 0.8400  

CD3C365
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C365 D4 T 2 2 100.0 Parallel CD3C3

Pin Nail Net Name
1 1032 H_D3B_VREFCA
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2390 CD3C365/CD3C3 4.700uF 7.700uF 0 C 1 1032 0 12.320uF 4.620uF 6.340uF 0.0039 330.75 147.38 12.320 4.6200  

CD3C38
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C38 F4 T 2 2 100.0 Parallel CD3C33

Pin Nail Net Name
1 1570 H_D3A_VREFDQ
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2386 CD3C38/CD3C33 4.700uF 5.000uF 0 C 1 1570 0 8.000uF 3.000uF 3.730uF 0.0011 728.09 212.31 8.0000 3.0000  

CD3C40
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C40 F4 T 2 2 100.0 Parallel CD3C34

Pin Nail Net Name
1 1537 H_D3B_VREFDQ
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2383 CD3C40/CD3C34 4.700uF 9.600uF 0 C 1 1537 0 15.360uF 5.760uF 7.390uF 0.0048 334.69 113.35 15.360 5.7600  

CD3C46
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C46 F3 T 2 2 100.0  

Pin Nail Net Name
1 1630 H_D3A_VREFDQ_R
2 1578 N60799296

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2112 CD3C46? 0.0220uF 0.0220uF 2 C 1630 1578 1 0.0352uF 0.0132uF 0.0500uF 0.0000 203.87 251.41 0.0400 0.0100  

CD3C47
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C47 F4 T 2 2 100.0  

Pin Nail Net Name
1 1642 H_D3B_VREFDQ_R
2 1546 N60799295

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2113 CD3C47? 0.0220uF 0.0220uF 2 C 1642 1546 1 0.0352uF 0.0132uF 0.0500uF 0.0000 251.57 292.35 0.0400 0.0100  

CD3C48
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C48 E4 T 2 2 100.0  

Pin Nail Net Name
1 1629 H_D3_VREFCA
2 1418 N60799305

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2114 CD3C48? 0.0220uF 0.0220uF 2 C 1629 1418 1 0.0352uF 0.0132uF 0.0500uF 0.0000 263.85 295.39 0.0400 0.0100  

CPC101
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC101 F3 T 2 2 100.0  

Pin Nail Net Name
1 1599 P_GT_FBA_10
2 1598 P_GT_DIFFA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2046 CPC101 330.00pF 330.00pF 2 C 1599 1598 0 528.00pF 198.00pF 329.98pF 0.0547 1005.4 804.16 528.00 198.00  

CPC102
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC102 F3 T 2 2 100.0  

Pin Nail Net Name
1 1614 P_GT_COMPA_10
2 1599 P_GT_FBA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2021 CPC102 47.00pF 47.00pF 2 C 1614 1599 0 75.20pF 28.20pF 46.47pF 0.1972 39.714 30.877 75.200 28.200  

CPC103
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC103 F3 T 2 2 100.0  

Pin Nail Net Name
1 1614 P_GT_COMPA_10
2 1615 P_GT_FBA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2069 CPC103 2200.0pF 2200.0pF 2 C 1614 1615 0 3520.0pF 1320.0pF 2066.1pF 2.5089 146.14 99.125 3520.0 1320.0  

CPC104
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC104 F3 T 2 2 100.0  

Pin Nail Net Name
1 1628 P_VCORE_FB_10
2 1627 P_VCORE_DIFF_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2050 CPC104 680.00pF 680.00pF 2 C 1628 1627 0 1088.00pF 408.00pF 680.32pF 0.2735 414.34 331.86 1088.0 408.00  

CPC105
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC105 F3 T 2 2 100.0  

Pin Nail Net Name
1 1632 P_VCORE_COMP_10
2 1628 P_VCORE_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2020 CPC105 47.00pF 47.00pF 2 C 1632 1628 0 75.20pF 28.20pF 46.11pF 0.0394 198.57 151.31 75.200 28.200  

CPC106
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC106 F3 T 2 2 100.0  

Pin Nail Net Name
1 1632 P_VCORE_COMP_10
2 1631 P_VCORE_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2070 CPC106 2200.0pF 2200.0pF 2 C 1632 1631 0 3520.0pF 1320.0pF 2109.8pF 1.9642 186.68 134.03 3520.0 1320.0  

CPC107
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC107 F3 T 2 2 100.0  

Pin Nail Net Name
1 1608 P_VCORE_VCC5_20
2 1594 DGND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2363 CPC107 1.000uF 1.000uF 0 C 1608 1594 0 1.600uF 0.600uF 1.310uF 0.0018 90.408 51.990 1.6000 0.6000  

CPC108
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC108 F3 T 2 2 100.0  

Pin Nail Net Name
1 1619 P_GT_CSP2A_10
2 1658 P_GT_CSN2A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2228 CPC108 0.1000uF 0.1000uF 0 C 1619 1658 0 0.1600uF 0.0600uF 0.0900uF 0.0000 423.20 266.46 0.1600 0.0600  

CPC109
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC109 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1609 P_VCORE_VRMP_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2107 CPC109 0.01000uF 0.01000uF 2 C 1594 1609 0 0.01600uF 0.00600uF 0.01000uF 0.0000 1146.8 1031.4 0.0200 0.0100  

CPC110
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC110 F3 T 2 2 100.0  

Pin Nail Net Name
1 1621 P_GT_CSP1A_10
2 1645 P_GT_CSN1A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2231 CPC110 0.1000uF 0.1000uF 0 C 1621 1645 0 0.1600uF 0.0600uF 0.0900uF 0.0000 652.93 429.15 0.1600 0.0600  

CPC115
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC115 F3 T 2 2 100.0  

Pin Nail Net Name
1 1624 P_VCORE_CSP2_10
2 1327 P_VCORE_CSN2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2279 CPC115 0.1000uF 0.1000uF 0 C 1624 1327 0 0.1600uF 0.0600uF 0.0900uF 0.0004 40.986 24.311 0.1600 0.0600  

CPC116
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC116 F3 T 2 2 100.0  

Pin Nail Net Name
1 1625 P_VCORE_CSP1_10
2 1324 P_VCORE_CSN1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2286 CPC116 0.1000uF 0.1000uF 0 C 1625 1324 0 0.1600uF 0.0600uF 0.1000uF 0.0005 36.811 27.196 0.1600 0.0600  

CPC118
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC118 F3 T 2 2 100.0  

Pin Nail Net Name
1 1634 P_VCORE_CSP3_10
2 1183 P_VCORE_CSN3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2171 CPC118 0.1000uF 0.1000uF 0 C 1634 1183 0 0.1600uF 0.0600uF 0.0900uF 0.0000 634.33 339.04 0.1600 0.0600  

CPC121
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC121 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1606 P_VCORE_IOUT_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2047 CPC121 470.00pF 470.00pF 2 C 1594 1606 0 752.00pF 282.00pF 470.01pF 0.0000 146933728 117550744 752.00 282.00  

CPC122
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC122 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1620 P_GT_TMA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2179 CPC122 0.1000uF 0.1000uF 1 C 1 1620 0 0.1600uF 0.0600uF 0.0900uF 0.0001 273.09 190.20 0.1600 0.0600  

CPC123
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC123 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1611 P_GT_IOUTA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2048 CPC123 470.00pF 470.00pF 2 C 1594 1611 0 752.00pF 282.00pF 470.48pF 0.4738 165.34 132.61 752.00 282.00  

CPC124
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC124 F3 T 2 2 100.0 Parallel CPC114

Pin Nail Net Name
1 1647 P_GT_CSCOMPA_10
2 1617 P_GT_CSSUMA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2071 CPC124/CPC114 2200.0pF 2420.0pF 2 C 1647 1617 0 3872.0pF 1452.0pF 2223.5pF 2.9549 136.50 87.030 3872.0 1452.0  

CPC126
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC126 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1623 P_VCORE_TM_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2227 CPC126 0.1000uF 0.1000uF 1 C 1 1623 0 0.1600uF 0.0600uF 0.0900uF 0.0000 500.94 313.06 0.1600 0.0600  

CPC128
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC128 F3 T 2 2 100.0 Parallel CPC117

Pin Nail Net Name
1 1323 P_VCORE_CSCOMP_10
2 1635 P_VCORE_CSSUM_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2072 CPC128/CPC117 3300.0pF 3860.0pF 2 C 1323 1635 0 6176.0pF 2316.0pF 3690.5pF 1.4533 442.68 315.27 6176.0 2316.0  

CPC132
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC132 F3 T 2 2 100.0  

Pin Nail Net Name
1 1333 H_VSS_SENSE
2 1605 P_VCORE_VSN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2060 CPC132 1000.0pF 1000.0pF 2 C 1333 1605 0 1600.0pF 600.0pF 1001.6pF 0.7805 213.54 171.50 1600.0 600.00  

CPC133
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC133 F3 T 2 2 100.0  

Pin Nail Net Name
1 1333 H_VSS_SENSE
2 1339 H_VCC_SENSE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2061 CPC133 1000.0pF 1000.0pF 2 C 1333 1339 0 1600.0pF 600.0pF 952.7pF 60.885 2.7370 1.9310 1600.0 600.00  

CPC137
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC137 F3 T 2 2 100.0  

Pin Nail Net Name
1 1343 H_GT_VSS_SENSE
2 1600 P_GT_VSNA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2067 CPC137 1000.0pF 1000.0pF 2 C 1343 1600 0 1600.0pF 600.0pF 1506.7pF 1.5610 106.77 19.914 1600.0 600.00  

CPC138
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC138 F3 T 2 2 100.0  

Pin Nail Net Name
1 1343 H_GT_VSS_SENSE
2 1342 H_GT_VCC_SENSE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2068 CPC138 1000.0pF 1000.0pF 2 C 1343 1342 1340 1600.0pF 600.0pF 936.0pF 1.3519 123.29 82.851 1600.0 600.00  

CPC140
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC140 F2 T 2 2 100.0  

Pin Nail Net Name
1 1678 P_VCORE_VCC1_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2376 CPC140 1.000uF 1.000uF 0 C 1 1678 0 1.600uF 0.600uF 0.820uF 0.0021 80.200 35.217 1.6000 0.6000  

CPC141
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC141 F2 T 2 2 100.0  

Pin Nail Net Name
1 1676 P_VCORE_BST2_R_20
2 1319 P_VCORE_PHASE2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2267 CPC141 0.1000uF 0.1000uF 0 C 1676 1319 0 0.1600uF 0.0600uF 0.0900uF 0.0001 157.76 101.00 0.1600 0.0600  

CPC142
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC142 F2 T 2 2 100.0  

Pin Nail Net Name
1 1690 P_VCORE_VCC2_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2377 CPC142 1.000uF 1.000uF 0 C 1 1690 0 1.600uF 0.600uF 0.820uF 0.0007 230.72 99.258 1.6000 0.6000  

CPC143
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC143 F2 T 2 2 100.0  

Pin Nail Net Name
1 1692 P_VCORE_BST3_R_20
2 1199 P_VCORE_PHASE3_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2268 CPC143 0.1000uF 0.1000uF 0 C 1692 1199 0 0.1600uF 0.0600uF 0.0900uF 0.0001 262.40 177.11 0.1600 0.0600  

CPC144
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC144 F2 T 2 2 100.0  

Pin Nail Net Name
1 1688 P_VCORE_VCC3_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2378 CPC144 1.000uF 1.000uF 0 C 1 1688 0 1.600uF 0.600uF 0.870uF 0.0011 153.40 82.128 1.6000 0.6000  

CPC145
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC145 F2 T 2 2 100.0  

Pin Nail Net Name
1 1673 P_VCORE_BST1_R_20
2 1320 P_VCORE_PHASE1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2270 CPC145 0.1000uF 0.1000uF 0 C 1673 1320 0 0.1600uF 0.0600uF 0.0900uF 0.0001 169.32 113.90 0.1600 0.0600  

CPC193
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC193 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1225 P_VCORE_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2203 CPC193 0.1000uF 0.1000uF 0 C 1594 1225 2 0.1600uF 0.0600uF 0.1000uF 0.0000 433.18 306.48 0.1600 0.0600  

CPC201
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC201 F3 T 2 2 100.0  

Pin Nail Net Name
1 1650 P_GT_VCC1_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2356 CPC201 1.000uF 1.000uF 0 C 1 1650 0 1.600uF 0.600uF 0.890uF 0.0027 61.051 34.966 1.6000 0.6000  

CPC202
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC202 F2 T 2 2 100.0  

Pin Nail Net Name
1 1666 P_GT_VCC2_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2361 CPC202 1.000uF 1.000uF 0 C 1 1666 0 1.600uF 0.600uF 0.850uF 0.0022 75.545 37.290 1.6000 0.6000  

CPC203
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC203 F3 T 2 2 100.0  

Pin Nail Net Name
1 1641 P_GT_BST1_R_20
2 1657 P_GT_PHASE1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2123 CPC203 0.1000uF 0.1000uF 0 C 1641 1657 0 0.1600uF 0.0600uF 0.0900uF 0.0000 333.98 212.32 0.1600 0.0600  

CPC204
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC204 F2 T 2 2 100.0  

Pin Nail Net Name
1 1660 P_GT_BST2_R_20
2 1671 P_GT_PHASE2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2204 CPC204 0.1000uF 0.1000uF 0 C 1660 1671 0 0.1600uF 0.0600uF 0.1000uF 0.0001 182.26 127.86 0.1600 0.0600  

CPC210
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC210 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1550 P_VRM_PGD_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2224 CPC210 0.1000uF 0.1000uF 0 C 1594 1550 0 0.1600uF 0.0600uF 0.0800uF 0.0000 1227.2 452.97 0.1600 0.0600  

CPC412
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC412 B2 T 2 2 100.0 Parallel CPC546

Pin Nail Net Name
1 2 +3V
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2398 CPC412/CU31C1 10.00uF 11.70uF 4 C 1 2 0 18.72uF 7.02uF 14.29uF 0.0373 52.235 39.591 18.720 7.0200  

CPC414
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC414 B2 T 2 2 100.0  

Pin Nail Net Name
1 164 +3V_ATX
2 611 P_3V_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2274 CPC414 0.1000uF 0.1000uF 0 C 164 611 1 0.1600uF 0.0600uF 0.1200uF 0.0258 0.6470 0.5700 0.1600 0.0600  

CPC415
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC415 B2 T 2 2 100.0  

Pin Nail Net Name
1 610 P_+3V_OV_G1_10
2 609 P_+3V_OV_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2108 CPC415 0.01000uF 0.01000uF 1 C 609 610 0 0.01600uF 0.00600uF 0.01000uF 0.0000 786.92 544.89 0.0200 0.0100  

CPC418
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC418 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 628 P_+3V_OV_ER_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2277 CPC418 0.1000uF 0.1000uF 0 C 1 628 706 0.1600uF 0.0600uF 0.1000uF 0.0001 192.31 172.62 0.1600 0.0600  

CPC419
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC419 B2 T 2 2 100.0 Parallel CKC1

Pin Nail Net Name
1 164 +3V_ATX
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2404 CPC419/CKC1/N 10.00uF 10.10uF 4 C 1 164 0 16.16uF 6.06uF 8.26uF 0.0248 67.840 29.604 16.160 6.0600  

CPC530
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC530 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1500 P_VDDQ_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2073 CPC530 3300.0pF 3300.0pF 2 C 1 1500 0 5280.0pF 1980.0pF 3560.5pF 0.0001 10543427 10099200 5280.0 1980.0  

CPC531
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC531 F4 T 2 2 100.0  

Pin Nail Net Name
1 1509 P_VDDQ_OFS_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2115 CPC531 0.0220uF 0.0220uF 0 C 1 1509 0 0.0352uF 0.0132uF 0.0200uF 0.0000 243.14 169.58 0.0400 0.0100  

CPC532
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC532 F4 T 2 2 100.0  

Pin Nail Net Name
1 1496 P_VDDQ_VCC_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2355 CPC532 1.000uF 1.000uF 0 C 1 1496 0 1.600uF 0.600uF 0.850uF 0.0009 185.60 92.317 1.6000 0.6000  

CPC536
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC536 F4 T 2 2 100.0  

Pin Nail Net Name
1 1490 P_VDDQ_PHASE_20
2 1497 P_VDDQ_BOOT_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2282 CPC536 0.1000uF 0.1000uF 0 C 1490 1497 0 0.1600uF 0.0600uF 0.0900uF 0.0002 91.494 58.579 0.1600 0.0600  

CPC537
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC537 F4 T 2 2 100.0  

Pin Nail Net Name
1 1501 P_VDDQ_FB_C_10
2 1499 P_VDDQ_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2118 CPC537 0.0680uF 0.0680uF 0 C 1499 1501 1502 0.1088uF 0.0408uF 0.0700uF 0.0001 207.55 168.54 0.1100 0.0400  

CPC539
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC539 C4 T 2 2 100.0  

Pin Nail Net Name
1 903 P_VTT_DDR_REFIN_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2283 CPC539 0.1000uF 0.1000uF 0 C 1 903 0 0.1600uF 0.0600uF 0.0900uF 0.0001 198.74 123.10 0.1600 0.0600  

CPC549
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC549 C4 T 2 2 100.0 Parallel CPC553

Pin Nail Net Name
1 909 VTT_DDR
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2461 CPC549/CPC553 22.00uF 60.00uF 8 C 1 909 0 78.00uF 42.00uF 44.85uF 0.1994 30.084 4.7650 78.000 42.000  

CPC552
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC552 C4 T 2 2 100.0  

Pin Nail Net Name
1 901 P_VTT_DDR_REOUT_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2285 CPC552 0.1000uF 0.1000uF 0 C 1 901 0 0.1600uF 0.0600uF 0.0900uF 0.0004 42.904 24.542 0.1600 0.0600  

CPC605
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC605 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 402 P_+5VSB_ATX_OV_E_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2287 CPC605 0.1000uF 0.1000uF 0 C 1 402 706 0.1600uF 0.0600uF 0.1100uF 0.0001 135.50 125.07 0.1600 0.0600  

CPC606
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC606 C4 T 2 2 100.0  

Pin Nail Net Name
1 947 P_+5VSB_ATX_OV_B_10
2 952 P_+5VSB_ATX_OV_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2033 CPC606 100.00pF 100.00pF 2 C 947 952 0 160.00pF 60.00pF 100.12pF 0.2935 56.792 45.566 160.00 60.000  

CPC607
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC607 C4 T 2 2 100.0  

Pin Nail Net Name
1 970 +5VSB_ATX
2 946 P_5VSB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2119 CPC607 0.0680uF 0.0680uF 0 C 970 946 0 0.1088uF 0.0408uF 0.0600uF 0.0001 174.24 98.159 0.1100 0.0400  

CPC613
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC613 B4 T 2 2 100.0  

Pin Nail Net Name
1 423 +5VSB
2 409 P_5VSB_GATE_RC_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2109 CPC613 0.01000uF 0.01000uF 0 C 423 409 0 0.01600uF 0.00600uF 0.01000uF 0.0000 164.34 115.67 0.0200 0.0100  

CPC615
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC615 D4 T 2 2 100.0  

Pin Nail Net Name
1 973 P_+5VSB_DUAL_OV_B_10
2 975 P_+5VSB_DUAL_OV_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2034 CPC615 100.00pF 100.00pF 2 C 973 975 0 160.00pF 60.00pF 100.06pF 0.2453 67.936 54.423 160.00 60.000  

CPC616
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC616 D4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 976 P_+5VSB_DUAL_OV_E_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2291 CPC616 0.1000uF 0.1000uF 0 C 1 976 706 0.1600uF 0.0600uF 0.1100uF 0.0002 76.951 69.756 0.1600 0.0600  

CPC630
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC630 B4 T 2 2 100.0  

Pin Nail Net Name
1 406 P_5VSB_Q2_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2117 CPC630 0.0470uF 0.0470uF 0 C 1 406 0 0.0752uF 0.0282uF 0.0700uF 0.0001 144.12 58.362 0.0800 0.0300  

CPC715
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC715 A1 T 2 2 100.0 Parallel CL1U1C232

Pin Nail Net Name
1 706 +3VSB_ATX
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2439 CPC715/COU1C2 22.00uF 22.10uF 4 C 1 706 0 28.73uF 15.47uF 18.24uF 0.0000 19047864 7948802 28.730 15.470  

CPC731
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC731 B4 T 2 2 100.0  

Pin Nail Net Name
1 434 P_+1_0V_A_BST_R_20
2 433 P_+1_0V_A_SW_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2295 CPC731 0.1000uF 0.1000uF 0 C 434 433 0 0.1600uF 0.0600uF 0.0900uF 0.0000 399.95 278.13 0.1600 0.0600  

CPC732
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC732 B4 T 2 2 100.0  

Pin Nail Net Name
1 425 +1_0V_A_VCC_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2382 CPC732 2.200uF 2.200uF 0 C 1 425 0 3.520uF 1.320uF 1.330uF 0.0035 105.81 0.7900 3.5200 1.3200  

CPC733
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC733 B4 T 2 2 100.0 Parallel CPC735

Pin Nail Net Name
1 421 P_1_0A_L+5VSB_S
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2402 CPC733/CPC735 10.00uF 20.10uF 4 C 1 421 0 32.16uF 12.06uF 30.07uF 0.0787 42.572 8.8670 32.160 12.060  

CPC736
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC736 B4 T 2 2 100.0  

Pin Nail Net Name
1 436 P_+1_0V_A_VOUT_10
2 429 P_+1_0V_A_FBR_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2045 CPC736 220.00pF 220.00pF 2 C 429 436 0 352.00pF 132.00pF 213.62pF 1.3265 27.641 20.510 352.00 132.00  

CPC740
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC740 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 444 P_VCCST_VCCSFR_D1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2299 CPC740 0.1000uF 0.1000uF 0 C 1 444 0 0.1600uF 0.0600uF 0.0900uF 0.0002 90.976 58.573 0.1600 0.0600  

CPC743
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC743 B4 T 2 2 100.0 Parallel CTQ2C3

Pin Nail Net Name
1 1 GND
2 422 +5VDUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2301 CPC743/CTQ2C3 0.1000uF 0.1000uF 0 C 1 422 0 0.1600uF 0.0600uF 0.0900uF 0.0000 345.21 196.41 0.1600 0.0600  

CPC751
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC751 D1 T 2 2 100.0  

Pin Nail Net Name
1 1221 P_VCCSA_FB_C_10
2 1220 P_VCCSA_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2120 CPC751 0.0680uF 0.0680uF 1 C 1220 1221 0 0.1088uF 0.0408uF 0.0700uF 0.0000 445.02 382.50 0.1100 0.0400  

CPC752
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC752 D2 T 2 2 100.0  

Pin Nail Net Name
1 1198 P_VCCSA_PHASE_20
2 1205 P_VCCSA_BOOT_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2304 CPC752 0.1000uF 0.1000uF 0 C 1198 1205 0 0.1600uF 0.0600uF 0.0900uF 0.0001 239.73 146.37 0.1600 0.0600  

CPC757
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC757 D1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1219 P_VCCSA_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2074 CPC757 3300.0pF 3300.0pF 2 C 1 1219 0 5280.0pF 1980.0pF 3513.5pF 1.4533 378.46 351.73 5280.0 1980.0  

CPC759
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC759 D1 T 2 2 100.0  

Pin Nail Net Name
1 1217 P_VCCSA_OFS_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2116 CPC759 0.0220uF 0.0220uF 0 C 1 1217 0 0.0352uF 0.0132uF 0.0200uF 0.0000 114.03 93.691 0.0400 0.0100  

CPC760
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC760 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 430 P_+1_0V_A_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2375 CPC760 1.000uF 1.000uF 0 C 1 430 0 1.600uF 0.600uF 0.670uF 0.0021 80.567 11.114 1.6000 0.6000  

CPC803
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC803 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1584 P_+12V_3V_EN_B1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2237 CPC803 0.1000uF 0.1000uF 0 C 1 1584 0 0.1600uF 0.0600uF 0.0900uF 0.0001 196.64 131.44 0.1600 0.0600  

CPC804
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC804 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1596 P_+12V_3V_EN_B2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2238 CPC804 0.1000uF 0.1000uF 0 C 1 1596 0 0.1600uF 0.0600uF 0.0900uF 0.0000 641.40 379.06 0.1600 0.0600  

CPC807
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC807 F4 T 2 2 100.0  

Pin Nail Net Name
1 1550 P_VRM_PGD_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2063 CPC807 1000.0pF 1000.0pF 2 C 1 1550 0 1600.0pF 600.0pF 1001.8pF 0.4506 369.86 297.24 1600.0 600.00  

CU3CC194
Device Loc Side Total Pin Tested Coverage (%) Comment
CU3CC194 C2 T 2 2 100.0  

Pin Nail Net Name
1 795 U3C1_PSW_EN
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2151 CU3CC194 0.1000uF 0.1000uF 0 C 1 795 0 0.1600uF 0.0600uF 0.1000uF 0.0001 278.11 219.02 0.1600 0.0600  

CU3CCE1
Device Loc Side Total Pin Tested Coverage (%) Comment
CU3CCE1 C1 T 2 2 100.0 Parallel CESDU3CC1

Pin Nail Net Name
1 747 +5V_U3C_P1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2469 CU3CCE1/CESDU 100.00uF 100.00uF 4 C 1 747 0 130.00uF 70.00uF 94.39uF 0.3312 30.196 24.549 130.00 70.000  

CAC10
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC10 C1 T 2 2 100.0  

Pin Nail Net Name
1 718 A_SURR_R
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2031 CAC10 100.00pF 100.00pF 2 C 729 718 0 160.00pF 60.00pF 99.55pF 0.0657 253.49 200.51 160.00 60.000  

CAC11
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC11 C1 T 2 2 100.0  

Pin Nail Net Name
1 712 A_SIDE_L
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2023 CAC11 100.00pF 100.00pF 2 C 729 712 0 160.00pF 60.00pF 100.30pF 0.1015 164.16 132.30 160.00 60.000  

CAC12
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC12 C1 T 2 2 100.0  

Pin Nail Net Name
1 714 A_SIDE_R
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2026 CAC12 100.00pF 100.00pF 2 C 729 714 0 160.00pF 60.00pF 100.33pF 0.2630 63.373 51.114 160.00 60.000  

CAC17
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC17 A1 T 2 2 100.0  

Pin Nail Net Name
1 14 A_LINE_L_L
2 13 A_LINE_L_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2413 CAC17 10.00uF 10.00uF 4 C 14 13 0 16.00uF 6.00uF 8.05uF 0.0165 101.14 41.482 16.000 6.0000  

CAC18
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC18 A1 T 2 2 100.0  

Pin Nail Net Name
1 725 A_LINE_R_L
2 12 A_LINE_R_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2414 CAC18 10.00uF 10.00uF 4 C 725 12 0 16.00uF 6.00uF 8.45uF 0.0172 96.869 47.471 16.000 6.0000  

CAC19
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC19 A1 T 2 2 100.0  

Pin Nail Net Name
1 8 A_MIC1_L_L
2 15 A_MIC1_L_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2387 CAC19 4.700uF 4.700uF 0 C 8 15 0 7.520uF 2.820uF 3.170uF 0.0202 38.873 5.8660 7.5200 2.8200  

CAC20
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC20 A1 T 2 2 100.0  

Pin Nail Net Name
1 9 A_MIC1_R_L
2 21 A_MIC1_R_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2395 CAC20 4.700uF 4.700uF 4 C 21 9 0 7.520uF 2.820uF 3.390uF 0.0205 38.269 9.2080 7.5200 2.8200  

CAC21
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC21 A1 T 2 2 100.0  

Pin Nail Net Name
1 29 A_FMIC1_L_L
2 17 A_FMIC1_L_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2418 CAC21 10.00uF 10.00uF 4 C 29 17 0 16.00uF 6.00uF 8.31uF 0.0363 45.892 21.236 16.000 6.0000  

CAC22
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC22 A1 T 2 2 100.0  

Pin Nail Net Name
1 7 A_FMIC1_R_L
2 16 A_FMIC1_R_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2411 CAC22 10.00uF 10.00uF 4 C 7 16 0 16.00uF 6.00uF 8.18uF 0.0146 113.87 49.648 16.000 6.0000  

CAC24
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC24 C1 T 2 2 100.0 Parallel CAC23

Pin Nail Net Name
1 729 A_GND
2 717 A_CGND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2175 CAC24/CAC23/N 0.1000uF 0.1000uF 0 C 729 717 0 0.1600uF 0.0600uF 0.0800uF 0.0000 500.02 234.54 0.1600 0.0600  

CAC27
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC27 A1 T 2 2 100.0  

Pin Nail Net Name
1 63 A_JD_FRONT
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2022 CAC27 100.00pF 100.00pF 2 C 729 63 0 160.00pF 60.00pF 100.39pF 0.2328 71.588 57.836 160.00 60.000  

CAC3
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC3 C1 T 2 2 100.0  

Pin Nail Net Name
1 723 A_LOUT_L
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2024 CAC3 100.00pF 100.00pF 2 C 729 723 0 160.00pF 60.00pF 100.08pF 0.3742 44.545 35.704 160.00 60.000  

CAC37
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC37 A1 T 2 2 100.0 Parallel CAC15

Pin Nail Net Name
1 59 A_FMIC1_L
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2110 CAC37/CAC15/N 0.01000uF 0.01000uF 0 C 729 59 0 0.01600uF 0.00600uF 0.01000uF 0.0000 299.97 211.94 0.0200 0.0100  

CAC38
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC38 A1 T 2 2 100.0 Parallel CAC16

Pin Nail Net Name
1 60 A_FMIC1_R
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2111 CAC38/CAC16/N 0.01000uF 0.01000uF 0 C 729 60 0 0.01600uF 0.00600uF 0.01000uF 0.0000 486.55 316.58 0.0200 0.0100  

CAC4
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC4 C1 T 2 2 100.0  

Pin Nail Net Name
1 721 A_LOUT_R
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2027 CAC4 100.00pF 100.00pF 2 C 729 721 0 160.00pF 60.00pF 100.52pF 0.4656 35.794 29.011 160.00 60.000  

CAC7
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC7 C1 T 2 2 100.0  

Pin Nail Net Name
1 731 A_CEN
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2028 CAC7 100.00pF 100.00pF 2 C 729 731 0 160.00pF 60.00pF 99.76pF 0.1276 130.57 103.82 160.00 60.000  

CAC8
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC8 C1 T 2 2 100.0  

Pin Nail Net Name
1 733 A_LFE
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2029 CAC8 100.00pF 100.00pF 2 C 729 733 0 160.00pF 60.00pF 100.44pF 0.1196 139.38 112.73 160.00 60.000  

CAC9
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC9 C1 T 2 2 100.0  

Pin Nail Net Name
1 720 A_SURR_L
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2030 CAC9 100.00pF 100.00pF 2 C 729 720 0 160.00pF 60.00pF 99.89pF 0.2686 62.045 49.506 160.00 60.000  

CACE1
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE1 A1 T 2 2 100.0  

Pin Nail Net Name
1 52 A_LOUT_L_C
2 20 A_LOUT_L_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2401 CACE1 10.00uF 10.00uF 4 C 20 52 0 16.00uF 6.00uF 10.86uF 0.0246 67.885 65.954 16.000 6.0000  

CACE10
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE10 A1 T 2 2 100.0  

Pin Nail Net Name
1 33 A_HPOUT_R_C
2 32 A_HPOUT_R_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2465 CACE10 100.00uF 100.00uF 4 C 32 33 0 130.00uF 70.00uF 104.15uF 0.2103 47.559 40.976 130.00 70.000  

CACE2
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE2 A1 T 2 2 100.0  

Pin Nail Net Name
1 55 A_LOUT_R_C
2 724 A_LOUT_R_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2423 CACE2 10.00uF 10.00uF 4 C 55 724 0 16.00uF 6.00uF 10.47uF 0.0039 428.17 382.63 16.000 6.0000  

CACE3
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE3 A1 T 2 2 100.0  

Pin Nail Net Name
1 49 A_SIDE_L_L
2 48 A_SIDE_L_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2427 CACE3 10.00uF 10.00uF 4 C 48 49 0 16.00uF 6.00uF 8.14uF 0.0000 15172384 6491995 16.000 6.0000  

CACE4
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE4 A1 T 2 2 100.0  

Pin Nail Net Name
1 18 A_SIDE_R_L
2 71 A_SIDE_R_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2408 CACE4 10.00uF 10.00uF 4 C 18 71 0 16.00uF 6.00uF 8.38uF 0.0206 80.714 38.475 16.000 6.0000  

CACE5
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE5 A1 T 2 2 100.0  

Pin Nail Net Name
1 69 A_CEN_L
2 70 A_CEN_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2405 CACE5 10.00uF 10.00uF 4 C 69 70 0 16.00uF 6.00uF 8.27uF 0.0303 55.059 24.977 16.000 6.0000  

CACE6
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE6 A1 T 2 2 100.0  

Pin Nail Net Name
1 53 A_LFE_L
2 50 A_LFE_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2417 CACE6 10.00uF 10.00uF 4 C 53 50 0 16.00uF 6.00uF 8.40uF 0.0856 19.479 9.3460 16.000 6.0000  

CACE7
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE7 A1 T 2 2 100.0  

Pin Nail Net Name
1 726 A_SURR_L_L
2 68 A_SURR_L_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2429 CACE7 10.00uF 10.00uF 4 C 726 68 0 16.00uF 6.00uF 8.19uF 0.0186 89.378 39.201 16.000 6.0000  

CACE8
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE8 A1 T 2 2 100.0  

Pin Nail Net Name
1 22 A_SURR_R_L
2 51 A_SURR_R_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2422 CACE8 10.00uF 10.00uF 4 C 22 51 0 16.00uF 6.00uF 8.47uF 0.0038 436.60 215.29 16.000 6.0000  

CACE9
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE9 A1 T 2 2 100.0  

Pin Nail Net Name
1 56 A_HPOUT_L_C
2 31 A_HPOUT_L_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2468 CACE9 100.00uF 100.00uF 4 C 56 31 0 130.00uF 70.00uF 103.15uF 0.2218 45.085 40.353 130.00 70.000  

CAU1C238
Device Loc Side Total Pin Tested Coverage (%) Comment
CAU1C238 A1 T 2 2 100.0 Parallel CAU1C38

Pin Nail Net Name
1 24 +5VA
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2421 CAU1C238/CAU1 10.00uF 10.20uF 4 C 729 24 0 16.32uF 6.12uF 7.63uF 0.0264 64.413 19.014 16.320 6.1200  

CAU1C27
Device Loc Side Total Pin Tested Coverage (%) Comment
CAU1C27 A1 T 2 2 100.0 Parallel CAU1C227

Pin Nail Net Name
1 35 A_VREF
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2420 CAU1C27/CAU1C 10.00uF 10.00uF 4 C 729 35 0 16.00uF 6.00uF 8.17uF 0.0254 65.541 28.465 16.000 6.0000  

CAU1C3
Device Loc Side Total Pin Tested Coverage (%) Comment
CAU1C3 A1 T 2 2 100.0  

Pin Nail Net Name
1 39 A_REGREF
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2397 CAU1C3 10.00uF 10.00uF 4 C 1 39 0 16.00uF 6.00uF 8.21uF 0.0176 94.932 42.034 16.000 6.0000  

CBCN4
Device Loc Side Total Pin Tested Coverage (%) Comment
CBCN4 A1 T 8 8 100.0  

Pin Nail Net Name
1 111 LS_COM1_RI1_
2 1 GND
3 107 LS_COM1_DTR1_
4 1 GND
5 109 LS_COM1_CTS1_
6 1 GND
7 106 LS_COM1_TXD1
8 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2036 CBCN4_1_2 150.00pF 150.00pF 2 C 1 111 0 240.00pF 90.00pF 150.01pF 0.4130 60.530 48.429 240.00 90.000  
2037 CBCN4_3_4 150.00pF 150.00pF 2 C 1 107 0 240.00pF 90.00pF 150.39pF 0.2507 99.723 80.295 240.00 90.000  
2038 CBCN4_5_6 150.00pF 150.00pF 2 C 1 109 0 240.00pF 90.00pF 150.29pF 0.2507 99.723 80.163 240.00 90.000  
2039 CBCN4_7_8 150.00pF 150.00pF 2 C 1 106 0 240.00pF 90.00pF 150.10pF 0.4924 50.777 40.689 240.00 90.000  

CBCN5
Device Loc Side Total Pin Tested Coverage (%) Comment
CBCN5 A1 T 8 8 100.0  

Pin Nail Net Name
1 110 LS_COM1_RTS1_
2 1 GND
3 104 LS_COM1_RXD1
4 1 GND
5 108 LS_COM1_DSR1_
6 1 GND
7 105 LS_COM1_DCD1_
8 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2040 CBCN5_1_2 150.00pF 150.00pF 2 C 1 110 0 240.00pF 90.00pF 149.75pF 0.1972 126.75 100.97 240.00 90.000  
2041 CBCN5_3_4 150.00pF 150.00pF 2 C 1 104 0 240.00pF 90.00pF 150.07pF 0.1447 172.73 138.34 240.00 90.000  
2042 CBCN5_5_6 150.00pF 150.00pF 2 C 1 108 0 240.00pF 90.00pF 149.78pF 0.3587 69.690 55.549 240.00 90.000  
2043 CBCN5_7_8 150.00pF 150.00pF 2 C 1 105 0 240.00pF 90.00pF 150.07pF 0.3328 75.129 60.171 240.00 90.000  

CESDATC14
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDATC14 C4 T 2 2 100.0 Parallel CEATXC15

Pin Nail Net Name
1 1 GND
2 5 -12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2234 CESDATC14/CBU 0.1000uF 0.1000uF 0 C 1 5 0 0.1600uF 0.0600uF 0.0800uF 0.0002 110.27 34.156 0.1600 0.0600  

CESDC14
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC14 B3 T 2 2 100.0  

Pin Nail Net Name
1 527 S_VCORE_SHDN__10_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2062 CESDC14 1000.0pF 1000.0pF 2 C 1 527 0 1600.0pF 600.0pF 1001.8pF 0.9012 184.93 148.62 1600.0 600.00  

CESDC5
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC5 C2 T 2 2 100.0 Parallel CSC26

Pin Nail Net Name
1 1 GND
2 871 S_VCCST_PWRGD

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2064 CESDC5/CSC26/ 1000.0pF 1000.0pF 2 C 1 871 0 1600.0pF 600.0pF 1024.2pF 1.3519 123.29 104.60 1600.0 600.00  

CESDC8
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC8 A3 T 2 2 100.0  

Pin Nail Net Name
1 211 O_IOPWRBTN_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2065 CESDC8 1000.0pF 1000.0pF 2 C 1 211 0 1600.0pF 600.0pF 997.9pF 0.4506 369.86 294.36 1600.0 600.00  

CESDC9
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC9 A3 T 2 2 100.0  

Pin Nail Net Name
1 199 O_RSTCON_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2066 CESDC9 1000.0pF 1000.0pF 2 C 1 199 0 1600.0pF 600.0pF NA NA NA NA NA NA  

CESDOC205
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDOC205 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 225 HDLED-

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2245 CESDOC205 0.1000uF 0.1000uF 0 C 1 225 0 0.1600uF 0.0600uF 0.0800uF 0.0006 29.027 13.262 0.1600 0.0600  

CGC16
Device Loc Side Total Pin Tested Coverage (%) Comment
CGC16 E1 T 2 2 100.0 No Component

Pin Nail Net Name
1 1282 +5V_DVI_HDMI
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2255 CGC16/CGC5/NC 0.1000uF 0.1000uF 0 C 1 1282 0 0.1600uF 0.0600uF 0.0800uF 0.0001 134.52 63.759 0.1600 0.0600  

CGC525
Device Loc Side Total Pin Tested Coverage (%) Comment
CGC525 F1 T 2 2 100.0  

Pin Nail Net Name
1 1717 +5V_D_VGA
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2275 CGC525 0.1000uF 0.1000uF 0 C 1 1717 0 0.1600uF 0.0600uF 0.0800uF 0.0001 123.00 57.361 0.1600 0.0600  

CGU1C25
Device Loc Side Total Pin Tested Coverage (%) Comment
CGU1C25 F1 T 2 2 100.0 Parallel CGU1C401

Pin Nail Net Name
1 1699 +1_8V_IVDDO
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2409 CGU1C25/CGU1C 10.00uF 10.20uF 4 C 1 1699 0 16.32uF 6.12uF 7.11uF 0.0262 64.902 12.540 16.320 6.1200  

CHC7
Device Loc Side Total Pin Tested Coverage (%) Comment
CHC7 C2 T 2 2 100.0 Parallel CHC24

Pin Nail Net Name
1 842 VCCST_VCCSFR
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1893 CHC7/C 17.20uF 17.20uF 0 C 1 842 0 27.52uF 10.32uF NA NA NA NA NA NA  

CHTC1
Device Loc Side Total Pin Tested Coverage (%) Comment
CHTC1 D3 T 2 2 100.0 Parallel COC217

Pin Nail Net Name
1 788 H_TR
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2240 CHTC1/COC217/ 0.1000uF 0.1000uF 0 C 1 788 0 0.1600uF 0.0600uF 0.0900uF 0.0000 553.09 350.75 0.1600 0.0600  

CK1PC1
Device Loc Side Total Pin Tested Coverage (%) Comment
CK1PC1 B2 T 2 2 100.0 Parallel CK1U1C81

Pin Nail Net Name
1 605 +1_2V_EPCI
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2410 CK1PC1/CK1U1C 10.00uF 10.40uF 4 C 1 605 0 16.64uF 6.24uF 15.86uF 0.1111 15.598 2.3490 16.640 6.2400  

CO1C12
Device Loc Side Total Pin Tested Coverage (%) Comment
CO1C12 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 695 O_5V_IN_2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2035 CO1C12 100.00pF 100.00pF 2 C 1 695 0 160.00pF 60.00pF 100.16pF 0.2150 77.523 62.261 160.00 60.000  

CO1C32
Device Loc Side Total Pin Tested Coverage (%) Comment
CO1C32 B1 T 2 2 100.0  

Pin Nail Net Name
1 705 O_12V_IN_1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2055 CO1C32 1000.0pF 1000.0pF 2 C 1 705 0 1600.0pF 600.0pF 1000.8pF 0.7805 213.54 171.17 1600.0 600.00  

CO1C34
Device Loc Side Total Pin Tested Coverage (%) Comment
CO1C34 B1 T 2 2 100.0  

Pin Nail Net Name
1 697 O_5V_IN_1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2059 CO1C34 1000.0pF 1000.0pF 2 C 1 697 0 1600.0pF 600.0pF 1002.1pF 0.4506 369.86 297.43 1600.0 600.00  

COC2
Device Loc Side Total Pin Tested Coverage (%) Comment
COC2 E1 T 2 2 100.0  

Pin Nail Net Name
1 789 O_CPUFANIN
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2127 COC2 0.1000uF 0.1000uF 0 C 1 789 0 0.1600uF 0.0600uF 0.1000uF 0.0000 397.51 333.74 0.1600 0.0600  

COC202
Device Loc Side Total Pin Tested Coverage (%) Comment
COC202 A3 T 2 2 100.0  

Pin Nail Net Name
1 647 O_RSTCON__P
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2150 COC202 0.1000uF 0.1000uF 0 C 1 647 0 0.1600uF 0.0600uF 0.1200uF 0.0000 337.25 255.92 0.1600 0.0600  

COC206
Device Loc Side Total Pin Tested Coverage (%) Comment
COC206 A3 T 2 2 100.0  

Pin Nail Net Name
1 648 PWRBTN_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2056 COC206 1000.0pF 1000.0pF 2 C 1 648 0 1600.0pF 600.0pF 999.7pF 0.4506 369.86 295.70 1600.0 600.00  

COC3
Device Loc Side Total Pin Tested Coverage (%) Comment
COC3 B1 T 2 2 100.0  

Pin Nail Net Name
1 756 O_CHAFANIN1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2246 COC3 0.1000uF 0.1000uF 0 C 1 756 0 0.1600uF 0.0600uF 0.1100uF 0.0000 356.06 322.82 0.1600 0.0600  

COC301
Device Loc Side Total Pin Tested Coverage (%) Comment
COC301 F3 T 2 2 100.0  

Pin Nail Net Name
1 1652 O_CPUFANIN_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2276 COC301 0.1000uF 0.1000uF 0 C 1 1652 0 0.1600uF 0.0600uF 0.1500uF 0.0000 2025.1 455.76 0.1600 0.0600  

COC311
Device Loc Side Total Pin Tested Coverage (%) Comment
COC311 F3 T 2 2 100.0  

Pin Nail Net Name
1 1580 O_CHAFANIN1_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2293 COC311 0.1000uF 0.1000uF 0 C 1 1580 0 0.1600uF 0.0600uF 0.1500uF 0.0001 265.98 49.919 0.1600 0.0600  

COC321
Device Loc Side Total Pin Tested Coverage (%) Comment
COC321 C1 T 2 2 100.0  

Pin Nail Net Name
1 744 O_CHAFANIN2_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2309 COC321 0.1000uF 0.1000uF 0 C 1 744 0 0.1600uF 0.0600uF 0.1000uF 0.0000 684.02 573.16 0.1600 0.0600  

COC406
Device Loc Side Total Pin Tested Coverage (%) Comment
COC406 F1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1710 O_KB_DATA_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2032 COC406 100.00pF 100.00pF 2 C 1 1710 0 160.00pF 60.00pF 99.88pF 0.2753 60.530 48.273 160.00 60.000  

COC407
Device Loc Side Total Pin Tested Coverage (%) Comment
COC407 F1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1707 O_KB_CLK_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2025 COC407 100.00pF 100.00pF 2 C 1 1707 0 160.00pF 60.00pF 99.51pF 0.2103 79.252 62.628 160.00 60.000  

COC760
Device Loc Side Total Pin Tested Coverage (%) Comment
COC760 A1 T 2 2 100.0  

Pin Nail Net Name
1 95 N16715606
2 118 O_DEEP_S5_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2272 COC760 0.1000uF 0.1000uF 0 C 118 95 634 0.1600uF 0.0600uF 0.0800uF 0.0002 87.616 28.303 0.1600 0.0600  

COC761
Device Loc Side Total Pin Tested Coverage (%) Comment
COC761 A1 T 2 2 100.0  

Pin Nail Net Name
1 706 +3VSB_ATX
2 118 O_DEEP_S5_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2269 COC761 0.1000uF 0.1000uF 0 C 706 118 95 0.1600uF 0.0600uF 0.0900uF 0.0002 94.570 61.836 0.1600 0.0600  

COTC1
Device Loc Side Total Pin Tested Coverage (%) Comment
COTC1 A3 T 2 2 100.0  

Pin Nail Net Name
1 82 O_TR_MB
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2220 COTC1 0.1000uF 0.1000uF 0 C 1 82 0 0.1600uF 0.0600uF 0.0900uF 0.0000 2103.7 1269.4 0.1600 0.0600  

COU1C31
Device Loc Side Total Pin Tested Coverage (%) Comment
COU1C31 B1 T 2 2 100.0 Parallel COU1C231

Pin Nail Net Name
1 1 GND
2 670 O_+1_8VA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2124 COU1C31/COU1C 0.1000uF 0.1000uF 0 C 1 670 0 0.1600uF 0.0600uF 0.0800uF 0.0001 149.85 74.679 0.1600 0.0600  

COU1C45
Device Loc Side Total Pin Tested Coverage (%) Comment
COU1C45 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 693 +3V_BAT_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2142 COU1C45 0.1000uF 0.1000uF 0 C 1 693 0 0.1600uF 0.0600uF 0.0900uF 0.0001 224.48 118.75 0.1600 0.0600  

COU1C53
Device Loc Side Total Pin Tested Coverage (%) Comment
COU1C53 B1 T 2 2 100.0 Parallel COU1C253

Pin Nail Net Name
1 1 GND
2 703 O_VREF_SIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2144 COU1C53/COU1C 0.1000uF 0.1000uF 0 C 1 703 0 0.1600uF 0.0600uF 0.1000uF 0.0001 156.28 140.54 0.1600 0.0600  

COU310C1
Device Loc Side Total Pin Tested Coverage (%) Comment
COU310C1 F4 T 2 2 100.0 Parallel COC3

Pin Nail Net Name
1 1579 CHAFANPWR
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2412 COU310C1/COC3 10.00uF 10.00uF 4 C 1579 1 0 16.00uF 6.00uF 6.54uF 0.0129 129.38 14.040 16.000 6.0000  

COU310C4
Device Loc Side Total Pin Tested Coverage (%) Comment
COU310C4 F4 T 2 2 100.0  

Pin Nail Net Name
1 1548 O_CHAFAN_VSET1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2381 COU310C4 1.000uF 1.000uF 0 C 1 1548 0 1.600uF 0.600uF 0.920uF 0.0023 71.882 45.420 1.6000 0.6000  

COU320C1
Device Loc Side Total Pin Tested Coverage (%) Comment
COU320C1 C1 T 2 2 100.0 Parallel COC3

Pin Nail Net Name
1 745 CHAFANPWR2
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2400 COU320C1/COC3 10.00uF 10.00uF 4 C 1 745 0 16.00uF 6.00uF 6.62uF 0.0147 113.48 14.124 16.000 6.0000  

COU320C4
Device Loc Side Total Pin Tested Coverage (%) Comment
COU320C4 C1 T 2 2 100.0  

Pin Nail Net Name
1 741 O_CHAFAN_VSET2
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2366 COU320C4 1.000uF 1.000uF 0 C 1 741 0 1.600uF 0.600uF 0.880uF 0.0015 111.45 61.877 1.6000 0.6000  

CPCE100
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE100 E1 T 2 2 100.0 Parallel CBC6

Pin Nail Net Name
1 1316 +12V_CPU
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2470 CPCE100/CBC6/ 270.00uF 1086.0uF 8 C 1 1316 0 1411.8uF 977.4uF 1025.6uF 3.9311 18.417 4.0900 1411.8 977.40  

CPCE108
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE108 E2 T 2 2 100.0 Parallel CPC175

Pin Nail Net Name
1 1181 VCORE
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2485 CPCE108/CPC16 560.00uF 3064.0uF 8 C 1 1181 0 3983.2uF 2757.6uF 2788.6uF 5.5677 36.688 1.8570 3983.2 2757.6  

CPCE207
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE207 F3 T 2 2 100.0 Parallel CPC218

Pin Nail Net Name
1 1340 VCCGT
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2475 CPCE207/CPC21 560.00uF 2460.0uF 8 C 1 1340 0 3198.0uF 2214.0uF 2281.3uF 1.2027 136.36 18.646 3198.0 2214.0  

CPCE514
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE514 E3 T 2 2 100.0 Parallel CD3C9

Pin Nail Net Name
1 1108 VDDQ
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2482 CPCE514/CD3C9 560.00uF 1723.0uF 8 C 1 1108 0 2239.9uF 1550.7uF 1688.7uF 4.8923 23.479 9.4000 2239.9 1550.7  

CPCE518
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE518 F4 T 2 2 100.0 Parallel CUCE5

Pin Nail Net Name
1 1495 P_VDDQ_REGIN_S
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2479 CPCE518/CPC54 560.00uF 760.00uF 8 C 1 1495 0 988.00uF 684.00uF 721.49uF 2.4366 20.794 5.1290 988.00 684.00  

CPCE707
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE707 D2 T 2 2 100.0 Parallel CHC10

Pin Nail Net Name
1 1184 VCCSA
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2480 CPCE707/CHC10 560.00uF 1208.0uF 8 C 1 1184 0 1570.4uF 1087.2uF 1106.2uF 2.5123 32.055 2.5260 1570.4 1087.2  

CSC3
Device Loc Side Total Pin Tested Coverage (%) Comment
CSC3 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 275 VCC_RTCEXT_CAP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2273 CSC3 0.1000uF 0.1000uF 0 C 1 275 0 0.1600uF 0.0600uF 0.0900uF 0.0001 240.69 127.66 0.1600 0.0600  

CSC59
Device Loc Side Total Pin Tested Coverage (%) Comment
CSC59 A3 T 2 2 100.0  

Pin Nail Net Name
1 289 S_RTCRST_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2354 CSC59 1.000uF 1.000uF 0 C 1 289 0 1.600uF 0.600uF 0.890uF 0.0019 87.764 50.125 1.6000 0.6000  

CSC60
Device Loc Side Total Pin Tested Coverage (%) Comment
CSC60 A3 T 2 2 100.0  

Pin Nail Net Name
1 253 S_SRTCRST_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2358 CSC60 1.000uF 1.000uF 0 C 1 253 0 1.600uF 0.600uF 0.880uF 0.0010 159.31 89.407 1.6000 0.6000  

CSQ40C1
Device Loc Side Total Pin Tested Coverage (%) Comment
CSQ40C1 A3 T 2 2 100.0 Parallel CPC612

Pin Nail Net Name
1 200 S_PWROK
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2126 CSQ40C1/CESDC 0.1000uF 0.1000uF 1 C 1 200 356 0.1600uF 0.0600uF 0.0900uF 0.0004 43.555 27.196 0.1600 0.0600  

CUCE6
Device Loc Side Total Pin Tested Coverage (%) Comment
CUCE6 A2 T 2 2 100.0 Parallel CEMIC22

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2466 CUCE6/CEMIC22 100.00uF 760.80uF 8 C 1 1229 0 989.04uF 684.72uF 719.21uF 1.9812 25.601 5.8030 989.04 684.72  

CXCE1
Device Loc Side Total Pin Tested Coverage (%) Comment
CXCE1 B1 T 2 2 100.0 Parallel CBU3C1

Pin Nail Net Name
1 4 +12V
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2474 CXCE1/CBU3C1/ 270.00uF 272.10uF 4 C 1 4 0 353.73uF 190.47uF 275.74uF 0.4727 57.564 54.999 353.73 190.47