Resistor Tested Devices

RL1R1 RL1R17 RL1R2 RL1R3 RL1R5 RL1R6 RL1R85 RD3R1 RD3R109 RD3R21
RD3R22 RD3R23 RD3R3 RD3R6 RD3R7 RD3R8 RU31U5R10 RU31U6R10 RU31U6R12 RU31U6R13
RU31U6R2 RU31U6R3 RU31U6R5 RU31U6R6 RU31U6R9 RU3CR101 RU3CR107 RU3CR170 RU3CR171 RU3CR194
RU3CR195 RU3CR9 RU3ER14 RU3ER17 RU3ER18 LAL1 LAL10 LAL11 LAL12 LAL13
LAL14 LAL15 LAL16 LAL2 LAL3 LAL4 LAL7 LAL8 LAL9 RAR1
RAR10 RAR100 RAR11 RAR12 RAR13 RAR14 RAR15 RAR16 RAR17 RAR2
RAR29 RAR3 RAR30 RAR4 RAR5 RAR6 RAR7 RAR8 RAR9 RARN1
RARN2 RBRN10 REATXR16 REATXR216 RGR129 RGR130 RGR131 RGR132 RGR133 RGR134
RGR135 RGR136 RGR1471 RGR1472 RGR1473 RGR1478 RGR1479 RGR151 RGR201 RGR202
RGR203 RGR212 RGR213 RGR215 RGR217 RGR251 RGR502 RGR503 RGR69 RGR70
RGUR12 RHR1 RHR105 RHR202 RHR203 RHR208 RHR209 RHR210 RHR217 RHR218
RHR52 RHR61 RHR90 RHR96 RHTR1 RK1PR1 RK1PR2 RK1R1 RK1R3 RK1R6
RK1R7 RKR1 RKR2 RKRP1 RKRP2 RO1R1 RO1R10 RO1R12 RO1R13 RO1R14
RO1R17 RO1R18 RO1R19 RO1R2 RO1R21 RO1R23 RO1R24 RO1R25 RO1R3 RO1R30
RO1R31 RO1R32 RO1R33 RO1R34 RO1R35 RO1R4 RO1R40 RO1R43 RO1R44 RO1R6
RO1R7 RO1R97 RO1RN2 ROR202 ROR204 ROR217 ROR218 ROR300 ROR301 ROR302
ROR303 ROR310 ROR311 ROR312 ROR313 ROR315 ROR318 ROR319 ROR320 ROR321
ROR322 ROR323 ROR325 ROR328 ROR329 ROR402 ROR403 ROR404 ROR405 ROR406
ROR407 ROR760 ROR761 ROR762 ROR763 RORN201 RORN202 RORN203 ROTR1 ROU310R4
ROU320R4 RPR101 RPR103 RPR104 RPR105 RPR106 RPR109 RPR111 RPR112 RPR113
RPR115 RPR117 RPR118 RPR122 RPR123 RPR125 RPR128 RPR129 RPR130 RPR132
RPR133 RPR134 RPR135 RPR137 RPR138 RPR139 RPR140 RPR141 RPR146 RPR147
RPR148 RPR149 RPR150 RPR153 RPR154 RPR155 RPR156 RPR157 RPR158 RPR159
RPR163 RPR164 RPR168 RPR169 RPR186 RPR187 RPR189 RPR195 RPR197 RPR198
RPR199 RPR201 RPR202 RPR207 RPR210 RPR224 RPR225 RPR307 RPR323 RPR328
RPR407 RPR413 RPR415 RPR416 RPR418 RPR421 RPR426 RPR429 RPR431 RPR508
RPR531 RPR533 RPR535 RPR537 RPR540 RPR542 RPR545 RPR546 RPR550 RPR551
RPR552 RPR553 RPR554 RPR556 RPR559 RPR560 RPR565 RPR567 RPR568 RPR599
RPR601 RPR603 RPR604 RPR605 RPR606 RPR607 RPR608 RPR609 RPR610 RPR611
RPR612 RPR613 RPR614 RPR615 RPR616 RPR617 RPR618 RPR619 RPR620 RPR621
RPR622 RPR623 RPR624 RPR625 RPR626 RPR627 RPR628 RPR630 RPR631 RPR632
RPR633 RPR634 RPR635 RPR636 RPR637 RPR639 RPR640 RPR641 RPR701 RPR702
RPR707 RPR708 RPR710 RPR712 RPR713 RPR717 RPR718 RPR739 RPR740 RPR741
RPR742 RPR743 RPR744 RPR747 RPR750 RPR755 RPR756 RPR759 RPR760 RPR762
RPR764 RPR767 RPR768 RPR801 RPR802 RPR803 RPR805 RPR808 RPR809 RPR812
RPR814 RPR815 RPR816 RPR817 RPR837 RPTR101 RPTR102 RPTR103 RPTR104 RSR10
RSR100 RSR11 RSR118 RSR119 RSR120 RSR121 RSR122 RSR125 RSR127 RSR129
RSR131 RSR134 RSR135 RSR14 RSR145 RSR152 RSR1607 RSR1628 RSR163 RSR1633
RSR1634 RSR1637 RSR1642 RSR1643 RSR166 RSR167 RSR18 RSR202 RSR22 RSR242
RSR3 RSR304 RSR34 RSR38 RSR4 RSR40 RSR42 RSR43 RSR44 RSR49
RSR5 RSR50 RSR52 RSR569 RSR57 RSR570 RSR571 RSR573 RSR574 RSR60
RSR616 RSR701 RSR73 RSR75 RSR801 RSR87 RSR9 RSR99 RSRN202 RSRN203
RSRN208 RSRN209 RSRN210 RSRN211 RSRN25 RSRN28 RUR730 RUR733 RUR755 RURN63
RURN64 RURN81 RURN82              

RL1R1
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R1 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 682 L1_LREXT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1192 RL1R1 2.490K 2.490K 2 R 1 682 0 2.739K 2.241K 2.500K 0.0016 51.972 49.987 2.7400 2.2400  

RL1R17
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R17 B1 T 2 2 100.0  

Pin Nail Net Name
1 634 +3VSB
2 288 CLKREQ__LAN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1303 RL1R17 8.200K 8.200K 2 R 634 288 0 9.020K 7.380K 8.230K 0.0057 47.842 46.037 9.0200 7.3800  

RL1R2
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R2 B1 T 2 2 100.0  

Pin Nail Net Name
1 685 L1_ISOLATE_
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1174 RL1R2 1.000K 1.000K 2 R 2 685 1 1.100K 0.900K 1.000K 0.0003 130.11 128.95 1.1000 0.9000  

RL1R3
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R3 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 685 L1_ISOLATE_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1448 RL1R3 15.00K 15.00K 2 R 1 685 2 16.50K 13.50K 15.26K 0.0103 48.548 40.210 16.500 13.500  

RL1R5
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R5 C1 T 2 2 100.0  

Pin Nail Net Name
1 683 L1_LINK1000__R
2 735 L1_LINK1000_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1093 RL1R5 300.00 300.00 2 R 735 683 0 420.00 180.00 302.64 0.0000 8583970 8395466 420.00 180.00  

RL1R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R6 D1 T 2 2 100.0  

Pin Nail Net Name
1 686 +3VSB_LAN1
2 1244 L1_ACTLEDP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1094 RL1R6 300.00 300.00 2 R 686 1244 0 420.00 180.00 302.50 0.2345 170.57 167.01 420.00 180.00  

RL1R85
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R85 B1 T 2 2 100.0  

Pin Nail Net Name
1 686 +3VSB_LAN1
2 692 S_WAKE__LAN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1304 RL1R85 8.200K 8.200K 2 R 686 692 0 9.020K 7.380K 8.220K 0.0000 6629250 6485570 9.0200 7.3800  

RD3R1
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R1 E4 T 2 2 100.0 Parallel RD3R2

Pin Nail Net Name
1 1094 H_D3A_VREFCA
2 1108 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1136 RD3R1/R 1.000K 0.500K 2 R 1108 1094 1 0.550K 0.450K 0.540K 0.0011 15.494 2.9680 0.5500 0.4500  

RD3R109
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R109 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1537 H_D3B_VREFDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1137 RD3R109 1.000K 1.000K 2 R 1537 1 1108 1.100K 0.900K 1.020K 0.0113 2.9370 2.4850 1.1000 0.9000  

RD3R21
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R21 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1578 N60799296

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1024 RD3R21 24.90 24.90 2 R 1 1578 0 34.86 14.94 26.08 0.0000 11064264 9753473 34.860 14.940  

RD3R22
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R22 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1546 N60799295

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1025 RD3R22 24.90 24.90 2 R 1 1546 0 34.86 14.94 26.07 0.0120 277.23 244.77 34.860 14.940  

RD3R23
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R23 E4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1418 N60799305

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1026 RD3R23 24.90 24.90 2 R 1 1418 0 34.86 14.94 25.97 0.0119 279.39 249.39 34.860 14.940  

RD3R3
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R3 D4 T 2 2 100.0 Parallel RD3R4

Pin Nail Net Name
1 1 GND
2 1094 H_D3A_VREFCA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1139 RD3R3/R 1.000K 0.500K 2 R 1 1094 1108 0.550K 0.450K 0.470K 0.0022 7.6680 2.5500 0.5500 0.4500  

RD3R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R6 F3 T 2 2 100.0  

Pin Nail Net Name
1 1570 H_D3A_VREFDQ
2 1108 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1141 RD3R6 1.000K 1.000K 2 R 1108 1570 1 1.100K 0.900K 1.050K 0.0076 4.3720 2.0880 1.1000 0.9000  

RD3R7
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R7 F4 T 2 2 100.0  

Pin Nail Net Name
1 1537 H_D3B_VREFDQ
2 1108 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1142 RD3R7 1.000K 1.000K 2 R 1108 1537 1 1.100K 0.900K 1.060K 0.0148 2.2460 0.9230 1.1000 0.9000  

RD3R8
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R8 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1570 H_D3A_VREFDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1145 RD3R8 1.000K 1.000K 2 R 1 1570 1108 1.100K 0.900K 0.970K 0.0056 5.9790 3.9100 1.1000 0.9000  

RU31U5R10
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U5R10 D1 T 2 2 100.0  

Pin Nail Net Name
1 752 U3C1_SEL
2 1243 +3VSD_U3C1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1231 RU31U5R10 2.700K 2.700K 2 R 1243 752 0 2.970K 2.430K 2.690K 0.0018 48.774 46.382 2.9700 2.4300  

RU31U6R10
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U6R10 C2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 770 U3C1_DFP_CC2_LREF

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1235 RU31U6R10 3.900K 3.900K 2 R 1 770 1229 4.290K 3.510K 3.980K 0.0000 2434318 1958728 4.2900 3.5100  

RU31U6R12
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U6R12 C2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 769 U3C1_DFP_CC2_HREF

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1449 RU31U6R12 15.00K 15.00K 2 R 1 769 1229 16.50K 13.50K 15.32K 0.0060 83.464 65.870 16.500 13.500  

RU31U6R13
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U6R13 C2 T 2 2 100.0  

Pin Nail Net Name
1 769 U3C1_DFP_CC2_HREF
2 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1442 RU31U6R13 12.00K 12.00K 2 R 1229 769 1 13.20K 10.80K 12.16K 0.0038 105.81 91.289 13.200 10.800  

RU31U6R2
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U6R2 C1 T 2 2 100.0  

Pin Nail Net Name
1 765 U3C1_DFP_CC1_HREF
2 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1443 RU31U6R2 12.00K 12.00K 2 R 1229 765 1 13.20K 10.80K 12.10K 0.0000 3534264 3228451 13.200 10.800  

RU31U6R3
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U6R3 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 765 U3C1_DFP_CC1_HREF

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1447 RU31U6R3 15.00K 15.00K 2 R 1 765 1229 16.50K 13.50K 15.72K 0.0126 39.583 20.557 16.500 13.500  

RU31U6R5
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U6R5 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 763 U3C1_DFP_CC1_LREF

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1236 RU31U6R5 3.900K 3.900K 2 R 1 763 1229 4.290K 3.510K 4.030K 0.0000 1786342 1190835 4.2900 3.5100  

RU31U6R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U6R6 C1 T 2 2 100.0  

Pin Nail Net Name
1 763 U3C1_DFP_CC1_LREF
2 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1459 RU31U6R6 20.00K 20.00K 2 R 1229 763 1 22.00K 18.00K 20.00K 0.0102 65.226 65.197 22.000 18.000  

RU31U6R9
Device Loc Side Total Pin Tested Coverage (%) Comment
RU31U6R9 C2 T 2 2 100.0  

Pin Nail Net Name
1 770 U3C1_DFP_CC2_LREF
2 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1457 RU31U6R9 20.00K 20.00K 2 R 1229 770 1 22.00K 18.00K 19.66K 0.0000 3187539 2652809 22.000 18.000  

RU3CR101
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3CR101 C1 T 2 2 100.0  

Pin Nail Net Name
1 764 U3C1_DFP_CC1
2 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1407 RU3CR101 10.00K 10.00K 2 R 1229 764 0 11.00K 9.00K 10.10K 0.0000 2066968 1870161 11.000 9.0000  

RU3CR107
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3CR107 C2 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 766 U3C1_DFP_CC2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1437 RU3CR107 10.00K 10.00K 2 R 1229 766 0 11.00K 9.00K 10.07K 0.0000 7908855 7390479 11.000 9.0000  

RU3CR170
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3CR170 C1 T 2 2 100.0  

Pin Nail Net Name
1 798 GP_TYPEC_CC_DETECT_1
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1391 RU3CR170 8.200K 8.200K 2 R 2 798 0 9.020K 7.380K 8.220K 0.0000 6629250 6485570 9.0200 7.3800  

RU3CR171
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3CR171 C2 T 2 2 100.0  

Pin Nail Net Name
1 799 GP_TYPEC_CC_DETECT_2
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1392 RU3CR171 8.200K 8.200K 2 R 2 799 0 9.020K 7.380K 8.240K 0.0000 1802483 1719964 9.0200 7.3800  

RU3CR194
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3CR194 C1 T 2 2 100.0  

Pin Nail Net Name
1 762 U3C1_DFP_CC_PIN_
2 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1393 RU3CR194 8.200K 8.200K 2 R 1229 762 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RU3CR195
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3CR195 C2 T 2 2 100.0  

Pin Nail Net Name
1 795 U3C1_PSW_EN
2 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1394 RU3CR195 8.200K 8.200K 2 R 1229 795 0 9.020K 7.380K 8.190K 0.0299 9.1420 9.0490 9.0200 7.3800  

RU3CR9
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3CR9 C2 T 2 2 100.0  

Pin Nail Net Name
1 797 S_USB3_OC_6
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1251 RU3CR9 4.700K 4.700K 2 R 634 797 0 5.170K 4.230K 4.710K 0.0000 2951674 2915861 5.1700 4.2300  

RU3ER14
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3ER14 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 849 GP_TYPEC_PWR_CTL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1173 RU3ER14 1.000K 1.000K 2 R 1 849 634 1.100K 0.900K 1.000K 0.0000 4893298 4864716 1.1000 0.9000  

RU3ER17
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3ER17 D1 T 2 2 100.0  

Pin Nail Net Name
1 1254 +5V_U3E_P1
2 796 S_USB3_OC_5

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1242 RU3ER17 4.700K 4.700K 2 R 1254 796 1 5.170K 4.230K 4.830K 0.0020 79.765 58.156 5.1700 4.2300  

RU3ER18
Device Loc Side Total Pin Tested Coverage (%) Comment
RU3ER18 D1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 796 S_USB3_OC_5

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1395 RU3ER18 8.200K 8.200K 2 R 1 796 1254 9.020K 7.380K 8.150K 0.0056 48.883 45.669 9.0200 7.3800  

LAL1
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL1 C1 T 2 2 100.0  

Pin Nail Net Name
1 14 A_LINE_L_L
2 727 A_LINE_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2492 LAL1 1.000K 1.000K 2 R 14 727 0 1.100K 0.900K 1.010K 0.0003 128.50 119.32 1.1000 0.9000  

LAL10
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL10 C1 T 2 2 100.0  

Pin Nail Net Name
1 22 A_SURR_R_L
2 718 A_SURR_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2494 LAL10 75.00 75.00 0 R 22 718 0 105.00 45.00 76.54 0.0000 7531294 7143658 105.00 45.000  

LAL11
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL11 C1 T 2 2 100.0  

Pin Nail Net Name
1 49 A_SIDE_L_L
2 712 A_SIDE_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2495 LAL11 75.00 75.00 0 R 49 712 0 105.00 45.00 76.60 0.0000 10419827 9863353 105.00 45.000  

LAL12
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL12 C1 T 2 2 100.0  

Pin Nail Net Name
1 18 A_SIDE_R_L
2 714 A_SIDE_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2496 LAL12 75.00 75.00 0 R 18 714 0 105.00 45.00 76.37 0.0000 9521143 9086368 105.00 45.000  

LAL13
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL13 A1 T 2 2 100.0  

Pin Nail Net Name
1 31 A_HPOUT_L_L
2 64 A_HPOUT_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2497 LAL13 75.00 75.00 0 R 31 64 0 105.00 45.00 76.14 0.0000 89677992 86277144 105.00 45.000  

LAL14
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL14 A1 T 2 2 100.0  

Pin Nail Net Name
1 32 A_HPOUT_R_L
2 61 A_HPOUT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2498 LAL14 75.00 75.00 0 R 32 61 0 105.00 45.00 76.20 0.0000 14066750 13506074 105.00 45.000  

LAL15
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL15 A1 T 2 2 100.0  

Pin Nail Net Name
1 29 A_FMIC1_L_L
2 59 A_FMIC1_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2499 LAL15 75.00 75.00 0 R 29 59 0 105.00 45.00 76.41 0.0335 298.33 284.32 105.00 45.000  

LAL16
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL16 A1 T 2 2 100.0  

Pin Nail Net Name
1 7 A_FMIC1_R_L
2 60 A_FMIC1_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2500 LAL16 75.00 75.00 0 R 7 60 0 105.00 45.00 76.41 0.0670 149.16 142.16 105.00 45.000  

LAL2
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL2 C1 T 2 2 100.0  

Pin Nail Net Name
1 725 A_LINE_R_L
2 730 A_LINE_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2493 LAL2 1.000K 1.000K 2 R 725 730 0 1.100K 0.900K 1.000K 0.0000 2812037 2803561 1.1000 0.9000  

LAL3
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL3 C1 T 2 2 100.0  

Pin Nail Net Name
1 20 A_LOUT_L_L
2 723 A_LOUT_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2501 LAL3 75.00 75.00 0 R 20 723 0 105.00 45.00 76.22 0.0335 298.33 286.24 105.00 45.000  

LAL4
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL4 C1 T 2 2 100.0  

Pin Nail Net Name
1 724 A_LOUT_R_L
2 721 A_LOUT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2502 LAL4 75.00 75.00 0 R 724 721 0 105.00 45.00 76.25 0.0000 6733820 6452390 105.00 45.000  

LAL7
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL7 C1 T 2 2 100.0  

Pin Nail Net Name
1 69 A_CEN_L
2 731 A_CEN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2505 LAL7 75.00 75.00 0 R 69 731 0 105.00 45.00 76.72 0.0000 96863304 91315360 105.00 45.000  

LAL8
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL8 C1 T 2 2 100.0  

Pin Nail Net Name
1 53 A_LFE_L
2 733 A_LFE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2506 LAL8 75.00 75.00 0 R 53 733 0 105.00 45.00 76.54 0.0000 7531294 7143658 105.00 45.000  

LAL9
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL9 C1 T 2 2 100.0  

Pin Nail Net Name
1 726 A_SURR_L_L
2 720 A_SURR_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2507 LAL9 75.00 75.00 0 R 726 720 0 105.00 45.00 76.14 0.0000 89677992 86277144 105.00 45.000  

RAR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR1 A1 T 2 2 100.0  

Pin Nail Net Name
1 729 A_GND
2 54 A_JDREF

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1458 RAR1 20.00K 20.00K 2 R 729 54 0 22.00K 18.00K 20.05K 0.0103 64.880 63.124 22.000 18.000  

RAR10
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR10 A1 T 2 2 100.0  

Pin Nail Net Name
1 63 A_JD_FRONT
2 30 A_SENSE_B

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1050 RAR10 47.00 47.00 2 R 30 63 0 65.80 28.20 48.05 0.0000 11501402 10859530 65.800 28.200  

RAR100
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR100 A1 T 2 2 100.0  

Pin Nail Net Name
1 47 AUDIO_LED_PWM
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1275 RAR100 8.200K 8.200K 2 R 634 47 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RAR11
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR11 A1 T 2 2 100.0  

Pin Nail Net Name
1 43 A_HD_SDIN0
2 41 A_HD_SDIN0_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1013 RAR11 22.00 22.00 0 R 41 43 0 30.80 13.20 23.01 0.0055 530.91 469.97 30.800 13.200  

RAR12
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR12 A1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 66 N16978758

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1084 RAR12 300.00 300.00 2 R 1229 66 0 420.00 180.00 302.09 0.2339 171.02 168.04 420.00 180.00  

RAR13
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR13 A1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 67 N16978835

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1085 RAR13 300.00 300.00 2 R 1229 67 0 420.00 180.00 302.64 0.0000 8583970 8395466 420.00 180.00  

RAR14
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR14 B1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 701 N16978863

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1086 RAR14 300.00 300.00 2 R 1229 701 0 420.00 180.00 302.64 0.0000 8583970 8395466 420.00 180.00  

RAR15
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR15 B1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 707 N16978891

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1087 RAR15 300.00 300.00 2 R 1229 707 0 420.00 180.00 303.04 0.0000 12343197 12030247 420.00 180.00  

RAR16
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR16 B1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 689 N16978919

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1088 RAR16 300.00 300.00 2 R 1229 689 0 420.00 180.00 301.82 0.0000 25364766 24979238 420.00 180.00  

RAR17
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR17 B1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 688 N16978947

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1089 RAR17 300.00 300.00 2 R 1229 688 0 420.00 180.00 303.86 0.0000 8283151 8016686 420.00 180.00  

RAR2
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR2 C1 T 2 2 100.0  

Pin Nail Net Name
1 19 A_SENSE_A
2 722 A_JD_LOUT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1263 RAR2 5.100K 5.100K 2 R 19 722 0 5.610K 4.590K 5.100K 0.0022 77.646 76.962 5.6100 4.5900  

RAR29
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR29 A1 T 2 2 100.0  

Pin Nail Net Name
1 8 A_MIC1_L_L
2 11 A_MIC1_L_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1151 RAR29 1.000K 1.000K 2 R 11 8 0 1.100K 0.900K 1.000K 0.0003 129.41 124.81 1.1000 0.9000  

RAR3
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR3 C1 T 2 2 100.0  

Pin Nail Net Name
1 19 A_SENSE_A
2 728 A_JD_LINE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1414 RAR3 10.00K 10.00K 2 R 19 728 0 11.00K 9.00K 10.06K 0.0085 39.088 36.718 11.000 9.0000  

RAR30
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR30 A1 T 2 2 100.0  

Pin Nail Net Name
1 9 A_MIC1_R_L
2 10 A_MIC1_R_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1154 RAR30 1.000K 1.000K 2 R 10 9 0 1.100K 0.900K 1.000K 0.0000 5703853 5483721 1.1000 0.9000  

RAR4
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR4 C1 T 2 2 100.0  

Pin Nail Net Name
1 19 A_SENSE_A
2 710 A_JD_MIC1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1451 RAR4 20.00K 20.00K 2 R 19 710 0 22.00K 18.00K 19.83K 0.0100 66.386 60.592 22.000 18.000  

RAR5
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR5 C1 T 2 2 100.0  

Pin Nail Net Name
1 19 A_SENSE_A
2 719 A_JD_SURR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1467 RAR5 39.20K 39.20K 2 R 19 719 0 43.12K 35.28K 39.62K 0.0265 49.356 44.049 43.120 35.280  

RAR6
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR6 C1 T 2 2 100.0  

Pin Nail Net Name
1 30 A_SENSE_B
2 713 A_JD_SIDE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1264 RAR6 5.100K 5.100K 2 R 30 713 0 5.610K 4.590K 5.120K 0.0000 19030704 18393176 5.6100 4.5900  

RAR7
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR7 C1 T 2 2 100.0  

Pin Nail Net Name
1 30 A_SENSE_B
2 732 A_JD_CNL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1417 RAR7 10.00K 10.00K 2 R 30 732 0 11.00K 9.00K 10.11K 0.0000 7589466 6753737 11.000 9.0000  

RAR8
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR8 A1 T 2 2 100.0  

Pin Nail Net Name
1 62 A_JD_FMIC1
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1453 RAR8 20.00K 20.00K 2 R 729 62 0 22.00K 18.00K 20.10K 0.0000 4457241 4230627 22.000 18.000  

RAR9
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR9 A1 T 2 2 100.0  

Pin Nail Net Name
1 65 A_JD_HPOUT
2 729 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1468 RAR9 39.20K 39.20K 2 R 729 65 0 43.12K 35.28K 39.93K 0.0000 2483198 2021105 43.120 35.280  

RARN1
Device Loc Side Total Pin Tested Coverage (%) Comment
RARN1 A1 T 8 4 50.0 No Test Nail

Pin Nail Net Name
1 25 A_VREF_MIC1_L
2 11 A_MIC1_L_R
3 34 A_VREF_MIC1_R
4 10 A_MIC1_R_R
5 0 NC_2114
6 0 NC_2115
7 0 NC_2116
8 0 NC_2117

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1193 RARN1/NP_5_6 2.700K 2.700K 2 R 0 0 0 2.970K 2.430K NA NA NA NA NA NA  
1194 RARN1/NP_7_8 2.700K 2.700K 2 R 0 0 0 2.970K 2.430K NA NA NA NA NA NA  
1195 RARN1_1_2 2.700K 2.700K 2 R 11 25 0 2.970K 2.430K 2.720K 0.0000 3362423 3138302 2.9700 2.4300  
1196 RARN1_3_4 2.700K 2.700K 2 R 10 34 0 2.970K 2.430K 2.730K 0.0000 4654829 4174852 2.9700 2.4300  

RARN2
Device Loc Side Total Pin Tested Coverage (%) Comment
RARN2 A1 T 8 8 100.0  

Pin Nail Net Name
1 27 A_VREF_FMIC1_R
2 7 A_FMIC1_R_L
3 26 A_VREF_FMIC1_L
4 29 A_FMIC1_L_L
5 6 A_VREF_FMIC2_L
6 31 A_HPOUT_L_L
7 28 A_VREF_FMIC2_R
8 32 A_HPOUT_R_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1197 RARN2_1_2 2.700K 2.700K 2 R 7 27 0 2.970K 2.430K 2.700K 0.0019 48.427 47.777 2.9700 2.4300  
1198 RARN2_3_4 2.700K 2.700K 2 R 29 26 0 2.970K 2.430K 2.710K 0.0019 48.081 47.001 2.9700 2.4300  
1199 RARN2_5_6 2.700K 2.700K 2 R 31 6 0 2.970K 2.430K 2.730K 0.0000 4654829 4174852 2.9700 2.4300  
1200 RARN2_7_8 2.700K 2.700K 2 R 32 28 0 2.970K 2.430K 2.720K 0.0000 4131889 3806386 2.9700 2.4300  

RBRN10
Device Loc Side Total Pin Tested Coverage (%) Comment
RBRN10 A2 T 8 6 75.0 No Test Nail

Pin Nail Net Name
1 634 +3VSB
2 96 S_PME_
3 0 NC_2173
4 0 NC_2174
5 111 LS_COM1_RI1_
6 112 N41678282
7 1 GND
8 112 N41678282

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1276 RBRN10/NP_3_ 8.200K 8.200K 2 R 0 0 0 9.020K 7.380K NA NA NA NA NA NA  
1277 RBRN10_1_2 8.200K 8.200K 2 R 634 96 0 9.020K 7.380K 8.030K 0.0000 3610417 2840748 9.0200 7.3800  
1278 RBRN10_5_6 8.200K 8.200K 2 R 112 111 1 9.020K 7.380K 8.170K 0.0056 48.650 46.605 9.0200 7.3800  
1279 RBRN10_7_8 8.200K 8.200K 2 R 1 112 111 9.020K 7.380K 8.180K 0.0000 3269887 3184234 9.0200 7.3800  

REATXR16
Device Loc Side Total Pin Tested Coverage (%) Comment
REATXR16 C4 T 2 2 100.0  

Pin Nail Net Name
1 967 ATX_PSON__R
2 847 O_PSON__O1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1031 REATXR16 33.00 33.00 2 R 847 967 0 46.20 19.80 35.24 0.0943 46.646 38.744 46.200 19.800  

REATXR216
Device Loc Side Total Pin Tested Coverage (%) Comment
REATXR216 C4 T 2 2 100.0  

Pin Nail Net Name
1 847 O_PSON__O1
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1456 REATXR216 20.00K 20.00K 2 R 970 847 0 22.00K 18.00K 19.95K 0.0102 65.573 63.866 22.000 18.000  

RGR129
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR129 E1 T 2 2 100.0  

Pin Nail Net Name
1 1723 H_DVI_TXDN2_C
2 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1096 RGR129 470.00 470.00 2 R 1297 1723 0 658.00 282.00 469.72 0.0000 13510255 13490236 658.00 282.00  

RGR130
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR130 E1 T 2 2 100.0  

Pin Nail Net Name
1 1722 H_DVI_TXDP2_C
2 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1097 RGR130 470.00 470.00 2 R 1297 1722 0 658.00 282.00 471.99 0.0000 9333830 9234899 658.00 282.00  

RGR131
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR131 E1 T 2 2 100.0  

Pin Nail Net Name
1 1724 H_DVI_TXDN1_C
2 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1098 RGR131 470.00 470.00 2 R 1297 1724 0 658.00 282.00 471.67 0.0000 8396213 8321771 658.00 282.00  

RGR132
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR132 E1 T 2 2 100.0  

Pin Nail Net Name
1 1725 H_DVI_TXDP1_C
2 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1099 RGR132 470.00 470.00 2 R 1297 1725 0 658.00 282.00 472.32 0.0000 10116834 9992047 658.00 282.00  

RGR133
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR133 E1 T 2 2 100.0  

Pin Nail Net Name
1 1731 H_DVI_TXDN0_C
2 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1100 RGR133 470.00 470.00 2 R 1297 1731 0 658.00 282.00 470.15 0.1868 335.45 335.18 658.00 282.00  

RGR134
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR134 E1 T 2 2 100.0  

Pin Nail Net Name
1 1730 H_DVI_TXDP0_C
2 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1101 RGR134 470.00 470.00 2 R 1297 1730 0 658.00 282.00 473.96 0.0000 11316204 11078026 658.00 282.00  

RGR135
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR135 E1 T 2 2 100.0  

Pin Nail Net Name
1 1280 H_DVI_TXCN_C
2 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1103 RGR135 470.00 470.00 2 R 1297 1280 0 658.00 282.00 470.80 0.1873 334.53 333.11 658.00 282.00  

RGR136
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR136 E1 T 2 2 100.0  

Pin Nail Net Name
1 1281 H_DVI_TXCP_C
2 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1104 RGR136 470.00 470.00 2 R 1297 1281 0 658.00 282.00 471.67 0.0000 8396213 8321771 658.00 282.00  

RGR1471
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR1471 E1 T 2 2 100.0  

Pin Nail Net Name
1 1296 VGA_BLUE
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1064 RGR1471 75.00 75.00 2 R 1 1296 0 105.00 45.00 75.99 0.0000 7742872 7486069 105.00 45.000  

RGR1472
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR1472 E1 T 2 2 100.0  

Pin Nail Net Name
1 1293 VGA_GREEN
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1065 RGR1472 75.00 75.00 2 R 1 1293 0 105.00 45.00 76.11 0.0496 201.64 194.18 105.00 45.000  

RGR1473
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR1473 E1 T 2 2 100.0  

Pin Nail Net Name
1 1295 VGA_RED
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1066 RGR1473 75.00 75.00 2 R 1 1295 0 105.00 45.00 76.08 0.0000 10852279 10461345 105.00 45.000  

RGR1478
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR1478 F1 T 2 2 100.0  

Pin Nail Net Name
1 1702 VGA_DDC_DATA
2 1288 VGA_DDC_DATA_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1070 RGR1478 100.00 100.00 2 R 1288 1702 0 140.00 60.00 101.63 0.0881 151.34 145.18 140.00 60.000  

RGR1479
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR1479 F1 T 2 2 100.0  

Pin Nail Net Name
1 1703 VGA_DDC_CLK
2 1719 VGA_DDC_CLK_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1071 RGR1479 100.00 100.00 2 R 1719 1703 0 140.00 60.00 101.48 0.0878 151.79 146.19 140.00 60.000  

RGR151
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR151 E1 T 2 2 100.0  

Pin Nail Net Name
1 1283 SW_DVI_HPD
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1455 RGR151 20.00K 20.00K 2 R 1 1283 0 22.00K 18.00K 20.12K 0.0000 2748309 2583993 22.000 18.000  

RGR201
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR201 D1 T 2 2 100.0  

Pin Nail Net Name
1 1255 SW_HDMI_DDC_DATA
2 1282 +5V_DVI_HDMI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1201 RGR201 2.700K 2.700K 2 R 1282 1255 0 2.970K 2.430K 2.710K 0.0000 5335873 5173355 2.9700 2.4300  

RGR202
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR202 D1 T 2 2 100.0  

Pin Nail Net Name
1 1256 SW_HDMI_DDC_CLK
2 1282 +5V_DVI_HDMI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1202 RGR202 2.700K 2.700K 2 R 1282 1256 0 2.970K 2.430K 2.710K 0.0000 1819453 1720183 2.9700 2.4300  

RGR203
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR203 E1 T 2 2 100.0  

Pin Nail Net Name
1 1299 G_LS_DDC_EN_HDMI
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1280 RGR203 8.200K 8.200K 2 R 2 1299 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RGR212
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR212 E1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1304 EQ_0

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1203 RGR212 2.700K 2.700K 2 R 1 1304 0 2.970K 2.430K 2.700K 0.0000 1830846 1797067 2.9700 2.4300  

RGR213
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR213 E1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1302 EQ_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1204 RGR213 2.700K 2.700K 2 R 1 1302 0 2.970K 2.430K 2.710K 0.0019 47.851 45.432 2.9700 2.4300  

RGR215
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR215 E1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1307 CG_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1205 RGR215 2.700K 2.700K 2 R 1 1307 0 2.970K 2.430K 2.710K 0.0000 2449052 2344982 2.9700 2.4300  

RGR217
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR217 E1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1308 REXT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1234 RGR217 3.000K 3.000K 2 R 1 1308 0 3.300K 2.700K 3.020K 0.0000 3102212 2859245 3.3000 2.7000  

RGR251
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR251 E1 T 2 2 100.0  

Pin Nail Net Name
1 742 S_DVI_HPD
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1500 RGR251 1.000M 1.000M 2 R 2 742 0 1.300M 0.700M 0.970M 0.0002 441.46 392.80 1.3000 0.7000  

RGR502
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR502 F1 T 2 2 100.0  

Pin Nail Net Name
1 1703 VGA_DDC_CLK
2 1717 +5V_D_VGA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1206 RGR502 2.700K 2.700K 2 R 1717 1703 0 2.970K 2.430K 2.700K 0.0000 1830846 1797067 2.9700 2.4300  

RGR503
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR503 F1 T 2 2 100.0  

Pin Nail Net Name
1 1702 VGA_DDC_DATA
2 1717 +5V_D_VGA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1207 RGR503 2.700K 2.700K 2 R 1717 1702 0 2.970K 2.430K 2.710K 0.0000 2449052 2344982 2.9700 2.4300  

RGR69
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR69 E1 T 2 2 100.0  

Pin Nail Net Name
1 1286 SW_DVI_DDC_CLK
2 1282 +5V_DVI_HDMI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1208 RGR69 2.700K 2.700K 2 R 1282 1286 0 2.970K 2.430K 2.710K 0.0000 1819453 1720183 2.9700 2.4300  

RGR70
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR70 E1 T 2 2 100.0  

Pin Nail Net Name
1 1285 SW_DVI_DDC_DATA
2 1282 +5V_DVI_HDMI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1209 RGR70 2.700K 2.700K 2 R 1282 1285 0 2.970K 2.430K 2.700K 0.0000 1830846 1797067 2.9700 2.4300  

RGUR12
Device Loc Side Total Pin Tested Coverage (%) Comment
RGUR12 F1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1294 N09933

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1077 RGUR12 200.00 200.00 2 R 1 1294 0 280.00 120.00 202.97 0.0000 17967712 17300020 280.00 120.00  

RHR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR1 C2 T 2 2 100.0  

Pin Nail Net Name
1 1115 H_HDA_SDI_R
2 873 H_HDA_SDI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1030 RHR1 33.00 33.00 2 R 873 1115 0 46.20 19.80 34.38 0.0000 7360157 6589171 46.200 19.800  

RHR105
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR105 C2 T 2 2 100.0  

Pin Nail Net Name
1 815 H_CPU_TRIGGER
2 1167 H_CPU_TRIGGER_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1010 RHR105 20.00 20.00 2 R 1167 815 0 28.00 12.00 21.36 0.0081 328.61 272.77 28.000 12.000  

RHR202
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR202 E2 T 2 2 100.0  

Pin Nail Net Name
1 1337 P_VCORE_VRHOT__R_10
2 842 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1167 RHR202 1.000K 1.000K 2 R 842 1337 0 1.100K 0.900K 1.010K 0.0000 1837571 1675994 1.1000 0.9000  

RHR203
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR203 D2 T 2 2 100.0  

Pin Nail Net Name
1 1171 H_THERMTRIP_
2 842 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1149 RHR203 1.000K 1.000K 2 R 842 1171 0 1.100K 0.900K 0.980K 0.0000 7105188 5797935 1.1000 0.9000  

RHR208
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR208 E2 T 2 2 100.0  

Pin Nail Net Name
1 1332 H_SVID_ALERT__R
2 1643 H_SVID_ALERT_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1080 RHR208 220.00 220.00 2 R 1643 1332 0 308.00 132.00 221.58 0.0000 8556547 8403107 308.00 132.00  

RHR209
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR209 E2 T 2 2 100.0  

Pin Nail Net Name
1 1643 H_SVID_ALERT_
2 842 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1063 RHR209 56.20 56.20 2 R 842 1643 0 78.68 33.72 57.80 0.0287 260.70 242.09 78.680 33.720  

RHR210
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR210 E2 T 2 2 100.0 Parallel RPR107

Pin Nail Net Name
1 842 VCCST_VCCSFR
2 1341 H_SVID_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1067 RHR210/RPR107 100.00 50.00 2 R 842 1341 0 70.00 30.00 51.42 0.0228 292.38 271.60 70.000 30.000  

RHR217
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR217 C2 T 2 2 100.0  

Pin Nail Net Name
1 819 H_PM_DOWN
2 1168 H_PM_DOWN_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1011 RHR217 20.00 20.00 2 R 1168 819 0 28.00 12.00 21.47 0.0082 325.25 265.58 28.000 12.000  

RHR218
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR218 E2 T 2 2 100.0  

Pin Nail Net Name
1 1337 P_VCORE_VRHOT__R_10
2 1336 H_PROCHOT__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1112 RHR218 499.00 499.00 2 R 1337 1336 0 698.60 299.40 503.65 0.0000 11642712 11371564 698.60 299.40  

RHR52
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR52 D2 T 2 2 100.0  

Pin Nail Net Name
1 878 VCCIO
2 1126 H_PEG_RCOMP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1022 RHR52 24.90 24.90 2 R 878 1126 0 34.86 14.94 26.02 0.0000 9465926 8403539 34.860 14.940  

RHR61
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR61 D2 T 2 2 100.0  

Pin Nail Net Name
1 1127 H_DP_RCOMP
2 878 VCCIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1023 RHR61 24.90 24.90 2 R 878 1127 0 34.86 14.94 26.12 0.0000 8682406 7617547 34.860 14.940  

RHR90
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR90 D2 T 2 2 100.0  

Pin Nail Net Name
1 1128 H_CFG_RCOMP
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1051 RHR90 49.90 49.90 2 R 1 1128 0 69.86 29.94 51.07 0.0225 295.80 278.48 69.860 29.940  

RHR96
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR96 D2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1156 H_CFG4

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1126 RHR96 1.000K 1.000K 2 R 1 1156 0 1.100K 0.900K 1.000K 0.0000 2602580 2560088 1.1000 0.9000  

RHTR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RHTR1 D3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 788 H_TR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1436 RHTR1 10.00K 10.00K 2 R 1 788 703 11.00K 9.00K 9.53K 0.0458 7.2720 3.8780 11.000 9.0000  

RK1PR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RK1PR1 B2 T 2 2 100.0  

Pin Nail Net Name
1 606 K1_1V2_FB_10
2 605 +1_2V_EPCI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1480 RK1PR1 51.00K 51.00K 2 R 605 606 1 56.10K 45.90K 51.80K 0.0000 4499076 3797522 56.100 45.900  

RK1PR2
Device Loc Side Total Pin Tested Coverage (%) Comment
RK1PR2 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 606 K1_1V2_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1488 RK1PR2 100.00K 100.00K 2 R 1 606 605 110.00K 90.00K 101.71K 0.0000 3820658 3168505 110.00 90.000  

RK1R1
Device Loc Side Total Pin Tested Coverage (%) Comment
RK1R1 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 595 K1_PEREXT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1444 RK1R1 12.10K 12.10K 2 R 1 595 0 13.31K 10.89K 12.02K 0.0000 2971016 2774965 13.310 10.890  

RK1R3
Device Loc Side Total Pin Tested Coverage (%) Comment
RK1R3 B2 T 2 2 100.0  

Pin Nail Net Name
1 572 K1_CLK100SEL
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1281 RK1R3 8.200K 8.200K 2 R 2 572 0 9.020K 7.380K 8.260K 0.0000 2788191 2593008 9.0200 7.3800  

RK1R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RK1R6 B2 T 2 2 100.0  

Pin Nail Net Name
1 570 CK_33M_SL1_R
2 120 CK_33M_SL1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1032 RK1R6 33.00 33.00 2 R 120 570 0 46.20 19.80 34.60 0.0000 23454054 20614288 46.200 19.800  

RK1R7
Device Loc Side Total Pin Tested Coverage (%) Comment
RK1R7 B2 T 2 2 100.0  

Pin Nail Net Name
1 571 K1_CLKRUN_EN_
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1282 RK1R7 8.200K 8.200K 2 R 2 571 0 9.020K 7.380K 8.210K 0.0000 2423629 2400208 9.0200 7.3800  

RKR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RKR1 B2 T 2 2 100.0  

Pin Nail Net Name
1 569 K_REQ_4
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1283 RKR1 8.200K 8.200K 2 R 2 569 0 9.020K 7.380K 8.220K 0.0000 6629250 6485570 9.0200 7.3800  

RKR2
Device Loc Side Total Pin Tested Coverage (%) Comment
RKR2 A2 T 2 2 100.0  

Pin Nail Net Name
1 547 K_REQ64_
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1284 RKR2 8.200K 8.200K 2 R 3 547 0 9.020K 7.380K 8.240K 0.0000 1802483 1719964 9.0200 7.3800  

RKRP1
Device Loc Side Total Pin Tested Coverage (%) Comment
RKRP1 A2 T 10 10 100.0 No Test Nail

Pin Nail Net Name
1 586 K_TRDY_
2 162 K_DEVSEL_
3 585 K_STOP_
4 163 K_LOCK_
5 2 +3V
6 174 K_SERR_
7 173 K_PERR_
8 587 K_FRAME_
9 161 K_IRDY_
10 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1285 RKRP1_1_10 8.200K 8.200K 2 R 2 586 0 9.020K 7.380K 8.120K 0.0000 4711689 4253970 9.0200 7.3800  
1286 RKRP1_2_10 8.200K 8.200K 2 R 2 162 0 9.020K 7.380K 8.320K 0.0058 46.813 39.716 9.0200 7.3800  
1287 RKRP1_3_10 8.200K 8.200K 2 R 2 585 0 9.020K 7.380K 8.140K 0.0000 5507231 5101857 9.0200 7.3800  
1288 RKRP1_4_10 8.200K 8.200K 2 R 2 163 0 9.020K 7.380K 8.160K 0.0000 13624904 12944239 9.0200 7.3800  
1289 RKRP1_5_10/NP 8.200K 8.200K 2 R 0 2 0 9.020K 7.380K NA NA NA NA NA NA  
1290 RKRP1_6_10 8.200K 8.200K 2 R 2 174 0 9.020K 7.380K 8.160K 0.0000 13624904 12944239 9.0200 7.3800  
1291 RKRP1_7_10 8.200K 8.200K 2 R 2 173 0 9.020K 7.380K 8.140K 0.0056 48.883 45.477 9.0200 7.3800  
1292 RKRP1_8_10 8.200K 8.200K 2 R 2 587 0 9.020K 7.380K 8.190K 0.0000 3352468 3304627 9.0200 7.3800  
1293 RKRP1_9_10 8.200K 8.200K 2 R 2 161 0 9.020K 7.380K 8.160K 0.0056 48.650 46.412 9.0200 7.3800  

RKRP2
Device Loc Side Total Pin Tested Coverage (%) Comment
RKRP2 A2 T 10 10 100.0 No Test Nail

Pin Nail Net Name
1 646 K_INTA_
2 645 K_INTC_
3 121 K_REQ_0
4 90 K_INTD_
5 2 +3V
6 91 K_INTB_
7 593 K_REQ_1
8 594 K_REQ_2
9 584 K_REQ_3
10 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1294 RKRP2_1_10 8.200K 8.200K 2 R 2 646 0 9.020K 7.380K 8.120K 0.0000 4711689 4253970 9.0200 7.3800  
1295 RKRP2_2_10 8.200K 8.200K 2 R 2 645 0 9.020K 7.380K 8.240K 0.0057 47.727 45.350 9.0200 7.3800  
1296 RKRP2_3_10 8.200K 8.200K 2 R 2 121 0 9.020K 7.380K 8.080K 0.0000 2208748 1890936 9.0200 7.3800  
1297 RKRP2_4_10 8.200K 8.200K 2 R 2 90 0 9.020K 7.380K 8.190K 0.0056 48.419 47.535 9.0200 7.3800  
1298 RKRP2_5_10/NP 8.200K 8.200K 2 R 0 2 0 9.020K 7.380K NA NA NA NA NA NA  
1299 RKRP2_6_10 8.200K 8.200K 2 R 2 91 0 9.020K 7.380K 8.090K 0.0055 49.466 43.117 9.0200 7.3800  
1300 RKRP2_7_10 8.200K 8.200K 2 R 2 593 0 9.020K 7.380K 8.100K 0.0000 2188027 1924212 9.0200 7.3800  
1301 RKRP2_8_10 8.200K 8.200K 2 R 2 594 0 9.020K 7.380K 8.110K 0.0056 49.232 44.064 9.0200 7.3800  
1302 RKRP2_9_10 8.200K 8.200K 2 R 2 584 0 9.020K 7.380K 8.140K 0.0000 5507231 5101857 9.0200 7.3800  

RO1R1
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R1 B1 T 2 2 100.0  

Pin Nail Net Name
1 198 O_RSMRST_
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1305 RO1R1 8.200K 8.200K 2 R 634 198 0 9.020K 7.380K 8.210K 0.0000 2423629 2400208 9.0200 7.3800  

RO1R10
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R10 B1 T 2 2 100.0  

Pin Nail Net Name
1 675 S_SLP_S4_
2 663 O_SLP_S4__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1083 RO1R10 300.00 300.00 2 R 675 663 0 420.00 180.00 302.64 0.0000 8583970 8395466 420.00 180.00  

RO1R12
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R12 B1 T 2 2 100.0  

Pin Nail Net Name
1 772 O_PWROK
2 673 O_PWROK_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1033 RO1R12 33.00 33.00 0 R 772 673 0 46.20 19.80 34.58 0.0000 11027396 9711397 46.200 19.800  

RO1R13
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R13 B1 T 2 2 100.0  

Pin Nail Net Name
1 662 O_RSTCON__P_R
2 647 O_RSTCON__P

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1150 RO1R13 1.000K 1.000K 2 R 647 662 0 1.100K 0.900K 1.000K 0.0000 3277550 3194885 1.1000 0.9000  

RO1R14
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R14 B1 T 2 2 100.0  

Pin Nail Net Name
1 669 O_PWRBTN__R
2 648 PWRBTN_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1153 RO1R14 1.000K 1.000K 2 R 648 669 0 1.100K 0.900K 1.000K 0.0000 4893298 4864716 1.1000 0.9000  

RO1R17
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R17 B1 T 2 2 100.0  

Pin Nail Net Name
1 199 O_RSTCON_
2 659 O1_RSTCON__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1060 RO1R17 49.90 49.90 2 R 199 659 0 69.86 29.94 51.89 0.0000 14563148 13113974 69.860 29.940  

RO1R18
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R18 B1 T 2 2 100.0  

Pin Nail Net Name
1 211 O_IOPWRBTN_
2 649 O1_IOPWRBTN__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1061 RO1R18 49.90 49.90 2 R 649 211 0 69.86 29.94 51.85 0.0000 17185702 15510139 69.860 29.940  

RO1R19
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R19 B1 T 2 2 100.0  

Pin Nail Net Name
1 98 O_PME_
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1306 RO1R19 8.200K 8.200K 2 R 634 98 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RO1R2
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R2 B1 T 2 2 100.0  

Pin Nail Net Name
1 649 O1_IOPWRBTN__R
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1162 RO1R2 1.000K 1.000K 2 R 634 649 0 1.100K 0.900K 1.000K 0.0003 129.65 125.99 1.1000 0.9000  

RO1R21
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R21 A1 T 2 2 100.0  

Pin Nail Net Name
1 84 O_PLED
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1307 RO1R21 8.200K 8.200K 2 R 634 84 0 9.020K 7.380K 8.220K 0.0057 47.957 46.533 9.0200 7.3800  

RO1R23
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R23 B1 T 2 2 100.0  

Pin Nail Net Name
1 694 O1_P46
2 678 +3V_BAT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1503 RO1R23 2.000M 2.000M 2 R 678 694 0 2.600M 1.400M 1.960M 0.0046 43.796 40.544 2.6000 1.4000  

RO1R24
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R24 B1 T 2 2 100.0  

Pin Nail Net Name
1 695 O_5V_IN_2
2 678 +3V_BAT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1504 RO1R24 2.000M 2.000M 2 R 678 695 0 2.600M 1.400M 1.940M 0.0000 9969443 8911662 2.6000 1.4000  

RO1R25
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R25 A1 T 2 2 100.0  

Pin Nail Net Name
1 74 O_KBRST_
2 660 O_KBRST__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1091 RO1R25 300.00 300.00 2 R 660 74 0 420.00 180.00 303.18 0.2358 169.65 165.16 420.00 180.00  

RO1R3
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R3 B1 T 2 2 100.0  

Pin Nail Net Name
1 659 O1_RSTCON__R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1308 RO1R3 8.200K 8.200K 2 R 2 659 0 9.020K 7.380K 8.210K 0.0000 2423629 2400208 9.0200 7.3800  

RO1R30
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R30 B1 T 2 2 100.0  

Pin Nail Net Name
1 704 O_VCORE_IN
2 652 O_VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1169 RO1R30 1.000K 1.000K 2 R 652 704 1 1.100K 0.900K 1.050K 0.0024 13.726 6.3580 1.1000 0.9000  

RO1R31
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R31 B1 T 2 2 100.0  

Pin Nail Net Name
1 704 O_VCORE_IN
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1170 RO1R31 1.000K 1.000K 2 R 1 704 652 1.100K 0.900K 1.050K 0.0003 117.51 54.827 1.1000 0.9000  

RO1R32
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R32 B1 T 2 2 100.0  

Pin Nail Net Name
1 705 O_12V_IN_1
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1441 RO1R32 11.00K 11.00K 2 R 4 705 1 12.10K 9.90K 11.08K 0.0063 58.431 53.925 12.100 9.9000  

RO1R33
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R33 B1 T 2 2 100.0  

Pin Nail Net Name
1 705 O_12V_IN_1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1171 RO1R33 1.000K 1.000K 2 R 1 705 0 1.100K 0.900K 0.920K 0.0000 2203329 507017 1.1000 0.9000  

RO1R34
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R34 B1 T 2 2 100.0  

Pin Nail Net Name
1 697 O_5V_IN_1
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1469 RO1R34 40.20K 40.20K 2 R 3 697 1229 44.22K 36.18K 41.21K 0.0143 93.592 70.061 44.220 36.180  

RO1R35
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R35 B1 T 2 2 100.0  

Pin Nail Net Name
1 697 O_5V_IN_1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1429 RO1R35 10.00K 10.00K 2 R 1 697 1229 11.00K 9.00K 10.40K 0.1190 2.8010 1.6730 11.000 9.0000  

RO1R4
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R4 B1 T 2 2 100.0  

Pin Nail Net Name
1 673 O_PWROK_R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1172 RO1R4 1.000K 1.000K 2 R 2 673 0 1.100K 0.900K 1.000K 0.0003 130.68 128.96 1.1000 0.9000  

RO1R40
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R40 A1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 87 O_COM1_RTS1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1121 RO1R40 680.00 680.00 2 R 1 87 0 952.00 408.00 682.03 0.0000 24003286 23824430 952.00 408.00  

RO1R43
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R43 A1 T 2 2 100.0  

Pin Nail Net Name
1 78 O_COM1_DTR1_
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1122 RO1R43 680.00 680.00 2 R 2 78 0 952.00 408.00 682.71 0.0000 8690068 8603561 952.00 408.00  

RO1R44
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R44 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 86 O_COM1_TXD1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1123 RO1R44 680.00 680.00 2 R 1 86 0 952.00 408.00 682.94 0.3939 230.17 227.69 952.00 408.00  

RO1R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R6 B1 T 2 2 100.0  

Pin Nail Net Name
1 648 PWRBTN_
2 706 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1309 RO1R6 8.200K 8.200K 2 R 706 648 0 9.020K 7.380K 8.200K 0.0057 48.188 48.107 9.0200 7.3800  

RO1R7
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R7 B1 T 2 2 100.0  

Pin Nail Net Name
1 647 O_RSTCON__P
2 706 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1310 RO1R7 8.200K 8.200K 2 R 706 647 0 9.020K 7.380K 8.140K 0.0097 28.256 26.176 9.0200 7.3800  

RO1R97
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R97 A1 T 2 2 100.0  

Pin Nail Net Name
1 1518 S_SLP_S3_
2 656 O1_PME_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1092 RO1R97 300.00 300.00 2 R 1518 656 0 420.00 180.00 306.20 0.2403 166.48 157.87 420.00 180.00  

RO1RN2
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1RN2 B1 T 8 4 50.0 No Test Nail

Pin Nail Net Name
1 777 O_X16_RST_
2 664 O_X16_RST__R
3 0 NC_1959
4 0 NC_1960
5 0 NC_1961
6 0 NC_1962
7 637 O_X1_RST_
8 665 O_X1_RST__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1036 RO1RN2_1_2 33.00 33.00 2 R 777 664 0 46.20 26.40 34.56 0.0000 5973398 4924810 46.200 26.400  
1037 RO1RN2/NP_3_ 33.00 33.00 2 R 0 0 0 46.20 26.40 NA NA NA NA NA NA  
1038 RO1RN2/NP_5_ 33.00 33.00 2 R 0 0 0 46.20 26.40 NA NA NA NA NA NA  
1039 RO1RN2_7_8 33.00 33.00 2 R 637 665 0 46.20 26.40 34.56 0.0000 5973398 4924810 46.200 26.400  

ROR202
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR202 A3 T 2 2 100.0  

Pin Nail Net Name
1 648 PWRBTN_
2 227 PWRBTN__PANEL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1040 ROR202 33.00 33.00 0 R 648 227 0 46.20 19.80 34.55 0.0000 16519509 14584440 46.200 19.800  

ROR204
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR204 A3 T 2 2 100.0  

Pin Nail Net Name
1 647 O_RSTCON__P
2 228 O_RSTCON__PR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1041 ROR204 33.00 33.00 2 R 647 228 0 46.20 19.80 35.11 0.0372 118.27 99.352 46.200 19.800  

ROR217
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR217 B1 T 2 2 100.0  

Pin Nail Net Name
1 788 H_TR
2 703 O_VREF_SIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1410 ROR217 10.00K 10.00K 2 R 703 788 1 11.00K 9.00K 10.09K 0.0086 38.859 35.351 11.000 9.0000  

ROR218
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR218 B1 T 2 2 100.0  

Pin Nail Net Name
1 82 O_TR_MB
2 703 O_VREF_SIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1411 ROR218 10.00K 10.00K 2 R 703 82 1 11.00K 9.00K 10.10K 0.0172 19.401 17.457 11.000 9.0000  

ROR300
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR300 F3 T 2 2 100.0  

Pin Nail Net Name
1 1652 O_CPUFANIN_R
2 789 O_CPUFANIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1210 ROR300 2.700K 2.700K 2 R 1652 789 1 2.970K 2.430K 2.740K 0.0209 4.3090 3.5990 2.9700 2.4300  

ROR301
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR301 F3 T 2 2 100.0  

Pin Nail Net Name
1 1652 O_CPUFANIN_R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1211 ROR301 2.700K 2.700K 2 R 2 1652 4 2.970K 2.430K 2.710K 0.0050 18.176 17.695 2.9700 2.4300  

ROR302
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR302 F1 T 2 2 100.0  

Pin Nail Net Name
1 1695 O_CPUFAN_PWM_B
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1212 ROR302 2.700K 2.700K 2 R 2 1695 0 2.970K 2.430K 2.710K 0.0000 2449052 2344982 2.9700 2.4300  

ROR303
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR303 F1 T 2 2 100.0  

Pin Nail Net Name
1 1653 O_CPUFAN_PWM_Q
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1213 ROR303 2.700K 2.700K 2 R 3 1653 0 2.970K 2.430K 2.650K 0.0000 3738988 3017807 2.9700 2.4300  

ROR310
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR310 F3 T 2 2 100.0  

Pin Nail Net Name
1 1580 O_CHAFANIN1_R
2 756 O_CHAFANIN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1214 ROR310 2.700K 2.700K 2 R 1580 756 1 2.970K 2.430K 2.710K 0.0206 4.3710 4.1660 2.9700 2.4300  

ROR311
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR311 F3 T 2 2 100.0  

Pin Nail Net Name
1 1580 O_CHAFANIN1_R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1215 ROR311 2.700K 2.700K 2 R 2 1580 756 2.970K 2.430K 2.700K 0.0243 3.7010 3.6380 2.9700 2.4300  

ROR312
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR312 F4 T 2 2 100.0  

Pin Nail Net Name
1 1514 GP_CHAFAN_PWM_DC_
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1216 ROR312 2.700K 2.700K 2 R 2 1514 0 2.970K 2.430K 2.720K 0.0019 47.621 44.255 2.9700 2.4300  

ROR313
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR313 F4 T 2 2 100.0  

Pin Nail Net Name
1 1581 O_CHAFAN_PWM_Q
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1217 ROR313 2.700K 2.700K 2 R 3 1581 0 2.970K 2.430K 2.690K 0.0000 5121738 4910920 2.9700 2.4300  

ROR315
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR315 F4 T 2 2 100.0  

Pin Nail Net Name
1 1516 O_CHAFAN_PWM_B
2 1514 GP_CHAFAN_PWM_DC_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1311 ROR315 8.200K 8.200K 2 R 1514 1516 0 9.020K 7.380K 8.240K 0.0000 1802483 1719964 9.0200 7.3800  

ROR318
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR318 F1 T 2 2 100.0  

Pin Nail Net Name
1 1694 O_CHAFAN_PWM
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1312 ROR318 8.200K 8.200K 2 R 4 1694 1 9.020K 7.380K 8.330K 0.0059 46.699 39.042 9.0200 7.3800  

ROR319
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR319 F1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1694 O_CHAFAN_PWM

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1218 ROR319 2.700K 2.700K 2 R 1 1694 4 2.970K 2.430K 2.930K 0.0022 40.993 5.9680 2.9700 2.4300  

ROR320
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR320 C1 T 2 2 100.0  

Pin Nail Net Name
1 744 O_CHAFANIN2_R
2 681 O_CHAFANIN2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1225 ROR320 2.700K 2.700K 2 R 744 681 0 2.970K 2.430K 2.710K 0.0019 47.851 45.625 2.9700 2.4300  

ROR321
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR321 C1 T 2 2 100.0  

Pin Nail Net Name
1 744 O_CHAFANIN2_R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1226 ROR321 2.700K 2.700K 2 R 2 744 0 2.970K 2.430K 2.670K 0.0018 49.356 44.032 2.9700 2.4300  

ROR322
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR322 B1 T 2 2 100.0  

Pin Nail Net Name
1 651 GP_CHAFAN_PWM_DC_2
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1227 ROR322 2.700K 2.700K 2 R 2 651 0 2.970K 2.430K 2.730K 0.0000 4654829 4174852 2.9700 2.4300  

ROR323
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR323 B1 T 2 2 100.0  

Pin Nail Net Name
1 743 O_CHAFAN_PWM2_Q
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1228 ROR323 2.700K 2.700K 2 R 3 743 0 2.970K 2.430K 2.700K 0.0000 1830846 1797067 2.9700 2.4300  

ROR325
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR325 B1 T 2 2 100.0  

Pin Nail Net Name
1 654 O_CHAFAN_PWM2_B
2 651 GP_CHAFAN_PWM_DC_2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1313 ROR325 8.200K 8.200K 2 R 651 654 0 9.020K 7.380K 8.220K 0.0000 6629250 6485570 9.0200 7.3800  

ROR328
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR328 C1 T 2 2 100.0  

Pin Nail Net Name
1 691 O_CHAFAN_PWM2
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1314 ROR328 8.200K 8.200K 2 R 4 691 1 9.020K 7.380K 8.330K 0.0000 1820144 1536726 9.0200 7.3800  

ROR329
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR329 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 691 O_CHAFAN_PWM2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1229 ROR329 2.700K 2.700K 2 R 1 691 4 2.970K 2.430K 2.660K 0.0000 2347240 2002916 2.9700 2.4300  

ROR402
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR402 F1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 1706 O_KB_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1247 ROR402 4.700K 4.700K 2 R 1229 1706 0 5.170K 4.230K 4.720K 0.0000 5846033 5654196 5.1700 4.2300  

ROR403
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR403 F1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 1696 O_KB_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1248 ROR403 4.700K 4.700K 2 R 1229 1696 0 5.170K 4.230K 4.740K 0.0000 3322136 3028506 5.1700 4.2300  

ROR404
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR404 B1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 668 O_MS_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1249 ROR404 4.700K 4.700K 2 R 1229 668 0 5.170K 4.230K 4.730K 0.0019 83.173 78.524 5.1700 4.2300  

ROR405
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR405 B1 T 2 2 100.0  

Pin Nail Net Name
1 1229 +5VSB_DUAL
2 667 O_MS_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1250 ROR405 4.700K 4.700K 2 R 1229 667 0 5.170K 4.230K 4.710K 0.0019 83.633 81.274 5.1700 4.2300  

ROR406
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR406 F1 T 2 2 100.0  

Pin Nail Net Name
1 1710 O_KB_DATA_R
2 1706 O_KB_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1042 ROR406 33.00 33.00 2 R 1710 1706 0 46.20 19.80 33.99 0.0000 34095884 31527348 46.200 19.800  

ROR407
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR407 F1 T 2 2 100.0  

Pin Nail Net Name
1 1707 O_KB_CLK_R
2 1696 O_KB_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1043 ROR407 33.00 33.00 2 R 1707 1696 0 46.20 19.80 34.26 0.0205 215.01 194.42 46.200 19.800  

ROR760
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR760 A1 T 2 2 100.0  

Pin Nail Net Name
1 95 N16715606
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1044 ROR760 33.00 33.00 2 R 634 95 0 46.20 19.80 34.16 0.0203 216.32 197.35 46.200 19.800  

ROR761
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR761 A1 T 2 2 100.0  

Pin Nail Net Name
1 97 O_DEEP_S5_12V
2 118 O_DEEP_S5_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1175 ROR761 1.000K 1.000K 2 R 118 97 0 1.100K 0.900K 1.010K 0.0000 1837571 1675994 1.1000 0.9000  

ROR762
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR762 A1 T 2 2 100.0  

Pin Nail Net Name
1 650 O_DEEP_S5
2 118 O_DEEP_S5_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1266 ROR762 5.600K 5.600K 2 R 650 118 706 6.160K 5.040K 5.650K 0.0117 15.934 14.587 6.1600 5.0400  

ROR763
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR763 B1 T 2 2 100.0  

Pin Nail Net Name
1 650 O_DEEP_S5
2 706 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1230 ROR763 2.700K 2.700K 2 R 706 650 118 2.970K 2.430K 2.720K 0.0000 3362423 3138302 2.9700 2.4300  

RORN201
Device Loc Side Total Pin Tested Coverage (%) Comment
RORN201 A4 T 8 4 50.0 No Test Nail

Pin Nail Net Name
1 0 NC_2177
2 0 NC_2178
3 371 O_PLED_R
4 84 O_PLED
5 0 NC_2179
6 0 NC_2180
7 370 S_SPKR_R
8 380 S_SPKR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1315 RORN201/NP_1 8.200K 8.200K 2 R 0 0 0 9.020K 7.380K NA NA NA NA NA NA  
1316 RORN201/NP_5 8.200K 8.200K 2 R 0 0 0 9.020K 7.380K NA NA NA NA NA NA  
1317 RORN201_3_4 8.200K 8.200K 2 R 84 371 0 9.020K 7.380K 8.140K 0.0000 5507231 5101857 9.0200 7.3800  
1318 RORN201_7_8 8.200K 8.200K 2 R 370 380 0 9.020K 7.380K 8.150K 0.0000 1777451 1667610 9.0200 7.3800  

RORN202
Device Loc Side Total Pin Tested Coverage (%) Comment
RORN202 A3 T 8 8 100.0 Parallel RORN202_3_4

Pin Nail Net Name
1 223 PLED+
2 422 +5VDUAL
3 223 PLED+
4 422 +5VDUAL
5 224 HDLED+
6 3 +5V
7 224 HDLED+
8 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1176 RORN202_1_2/R 1.000K 0.500K 2 R 422 223 0 0.550K 0.450K 0.500K 0.0002 80.023 74.347 0.5500 0.4500  
1177 RORN202_3_4/R 1.000K 0.500K 2 R 422 223 0 0.550K 0.450K NA NA NA NA NA NA  
1178 RORN202_5_6/R 1.000K 0.500K 2 R 3 224 0 0.550K 0.450K 0.500K 0.0000 2408271 2231640 0.5500 0.4500  
1179 RORN202_7_8/R 1.000K 0.500K 2 R 3 224 0 0.550K 0.450K NA NA NA NA NA NA  

RORN203
Device Loc Side Total Pin Tested Coverage (%) Comment
RORN203 A4 T 8 6 75.0 No Test Nail

Pin Nail Net Name
1 290 SPKO
2 363 SPKO-_R
3 0 NC_1963
4 0 NC_1964
5 230 +5V_SPKO
6 369 +5V_SPKO_R
7 3 +5V
8 369 +5V_SPKO_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1045 RORN203_1_2 33.00 33.00 2 R 290 363 0 46.20 26.40 34.57 0.0208 158.32 130.72 46.200 26.400  
1046 RORN203/NP_3 33.00 33.00 2 R 0 0 0 46.20 26.40 NA NA NA NA NA NA  
1047 RORN203_5_6 33.00 33.00 2 R 230 369 0 46.20 26.40 34.21 0.0000 16151576 12733852 46.200 26.400  
1048 RORN203_7_8 33.00 33.00 2 R 3 369 0 46.20 26.40 34.12 0.0203 162.57 126.82 46.200 26.400  

ROTR1
Device Loc Side Total Pin Tested Coverage (%) Comment
ROTR1 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 82 O_TR_MB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1427 ROTR1 10.00K 10.00K 2 R 1 82 703 11.00K 9.00K 9.84K 0.0294 11.344 9.5180 11.000 9.0000  

ROU310R4
Device Loc Side Total Pin Tested Coverage (%) Comment
ROU310R4 F4 T 2 2 100.0  

Pin Nail Net Name
1 1694 O_CHAFAN_PWM
2 1548 O_CHAFAN_VSET1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1494 ROU310R4 100.00K 100.00K 2 R 1694 1548 1 110.00K 90.00K 103.72K 2.4275 1.3730 0.8620 110.00 90.000  

ROU320R4
Device Loc Side Total Pin Tested Coverage (%) Comment
ROU320R4 C1 T 2 2 100.0  

Pin Nail Net Name
1 691 O_CHAFAN_PWM2
2 741 O_CHAFAN_VSET2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1489 ROU320R4 100.00K 100.00K 2 R 691 741 1 110.00K 90.00K 81.94K 42.930 0.0780 0.0630 110.00 90.000  

RPR101
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR101 F3 T 2 2 100.0  

Pin Nail Net Name
1 1603 P_VCORE_IOUT_10
2 1606 P_VCORE_IOUT_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1184 RPR101 1.300K 1.300K 2 R 1606 1603 0 1.430K 1.170K 1.300K 0.0011 37.861 37.665 1.4300 1.1700  

RPR103
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR103 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1639 P_GT_PWM1A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1491 RPR103 100.00K 100.00K 2 R 1594 1639 0 110.00K 90.00K 101.86K 0.0000 3868347 3149550 110.00 90.000  

RPR104
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR104 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1603 P_VCORE_IOUT_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1460 RPR104 24.90K 24.90K 2 R 1594 1603 0 27.39K 22.41K 25.04K 0.0160 51.857 48.999 27.390 22.410  

RPR105
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR105 F3 T 2 2 100.0  

Pin Nail Net Name
1 1609 P_VCORE_VRMP_10
2 1316 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1181 RPR105 1.000K 1.000K 2 R 1316 1609 0 1.100K 0.900K 1.000K 0.0000 2812037 2803561 1.1000 0.9000  

RPR106
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR106 F3 T 2 2 100.0  

Pin Nail Net Name
1 1592 P_GT_IOUTA_10
2 1594 DGND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1461 RPR106 24.90K 24.90K 2 R 1594 1592 0 27.39K 22.41K 25.01K 0.0160 51.972 49.685 27.390 22.410  

RPR109
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR109 F3 T 2 2 100.0  

Pin Nail Net Name
1 1330 H_SVID_CLK
2 842 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1049 RPR109 45.30 45.30 2 R 842 1330 0 63.42 27.18 47.21 0.0193 313.62 280.52 63.420 27.180  

RPR111
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR111 F3 T 2 2 100.0  

Pin Nail Net Name
1 1644 P_GT_PHASE1_10
2 1621 P_GT_CSP1A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1272 RPR111 6.800K 6.800K 2 R 1621 1644 0 7.480K 6.120K 6.550K 0.0477 4.7520 2.9870 7.4800 6.1200  

RPR112
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR112 F3 T 2 2 100.0  

Pin Nail Net Name
1 1619 P_GT_CSP2A_10
2 1659 P_GT_PHASE2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1273 RPR112 6.800K 6.800K 2 R 1659 1619 0 7.480K 6.120K 6.820K 0.0078 28.915 28.215 7.4800 6.1200  

RPR113
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR113 F3 T 2 2 100.0 Parallel RPR119

Pin Nail Net Name
1 1617 P_GT_CSSUMA_10
2 1659 P_GT_PHASE2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1483 RPR113/R 90.90K 45.45K 2 R 1617 1659 0 50.00K 40.91K 42.20K 0.8902 1.7020 0.4830 50.000 40.910  

RPR115
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR115 F3 T 2 2 100.0 Parallel RPR127

Pin Nail Net Name
1 1635 P_VCORE_CSSUM_10
2 1326 P_VCORE_PHASE2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1484 RPR115/R 90.90K 30.30K 2 R 1635 1326 0 33.33K 27.27K 27.90K 0.2074 4.8710 1.0160 33.330 27.270  

RPR117
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR117 F3 T 2 2 100.0  

Pin Nail Net Name
1 1625 P_VCORE_CSP1_10
2 1325 P_VCORE_PHASE1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1274 RPR117 6.800K 6.800K 2 R 1325 1625 0 7.480K 6.120K 6.730K 0.0038 59.279 53.509 7.4800 6.1200  

RPR118
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR118 F3 T 2 2 100.0  

Pin Nail Net Name
1 1624 P_VCORE_CSP2_10
2 1326 P_VCORE_PHASE2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1270 RPR118 6.800K 6.800K 2 R 1326 1624 0 7.480K 6.120K 6.730K 0.0038 59.279 53.509 7.4800 6.1200  

RPR122
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR122 F3 T 2 2 100.0  

Pin Nail Net Name
1 1626 P_VCORE_ILIM_10
2 1323 P_VCORE_CSCOMP_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1466 RPR122 37.40K 37.40K 2 R 1323 1626 0 41.14K 33.66K 38.04K 0.0000 5091530 4214260 41.140 33.660  

RPR123
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR123 F3 T 2 2 100.0  

Pin Nail Net Name
1 1613 P_GT_ILIMA_10
2 1647 P_GT_CSCOMPA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1472 RPR123 40.20K 40.20K 2 R 1647 1613 0 44.22K 36.18K 40.76K 0.0000 2926838 2518323 44.220 36.180  

RPR125
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR125 F3 T 2 2 100.0  

Pin Nail Net Name
1 1634 P_VCORE_CSP3_10
2 1182 P_VCORE_PHASE3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1271 RPR125 6.800K 6.800K 2 R 1182 1634 0 7.480K 6.120K 6.140K 0.0032 71.382 1.9240 7.4800 6.1200  

RPR128
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR128 F3 T 2 2 100.0  

Pin Nail Net Name
1 1333 H_VSS_SENSE
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1068 RPR128 100.00 100.00 2 R 1 1333 0 140.00 60.00 102.04 0.0000 8889371 8436542 140.00 60.000  

RPR129
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR129 F3 T 2 2 100.0  

Pin Nail Net Name
1 1605 P_VCORE_VSN_10
2 1333 H_VSS_SENSE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1187 RPR129 1.500K 1.500K 2 R 1333 1605 0 1.650K 1.350K 1.510K 0.0006 86.085 81.922 1.6500 1.3500  

RPR130
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR130 F3 T 2 2 100.0  

Pin Nail Net Name
1 1620 P_GT_TMA_10
2 1656 P_GT_TMA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1079 RPR130 205.00 205.00 2 R 1620 1656 0 287.00 123.00 204.88 0.1079 253.42 253.06 287.00 123.00  

RPR132
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR132 F3 T 2 2 100.0  

Pin Nail Net Name
1 1646 P_GT_CSPA_R_10
2 1617 P_GT_CSSUMA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1498 RPR132 300.00K 300.00K 2 R 1617 1646 1647 330.00K 270.00K 300.43K 0.0000 2530411 2493898 330.00 270.00  

RPR133
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR133 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1623 P_VCORE_TM_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1120 RPR133 680.00 680.00 2 R 1 1623 1674 952.00 408.00 687.28 1.0546 85.970 83.668 952.00 408.00  

RPR134
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR134 F3 T 2 2 100.0  

Pin Nail Net Name
1 1322 P_VCORE_CSP_R_10
2 1635 P_VCORE_CSSUM_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1497 RPR134 196.00K 196.00K 2 R 1635 1322 1323 215.60K 176.40K 199.01K 0.2581 25.311 21.427 215.60 176.40  

RPR135
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR135 F3 T 2 2 100.0  

Pin Nail Net Name
1 1339 H_VCC_SENSE
2 1181 VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1075 RPR135 100.00 100.00 2 R 1181 1339 0 140.00 60.00 102.35 0.0000 10613165 9990697 140.00 60.000  

RPR137
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR137 F3 T 2 2 100.0  

Pin Nail Net Name
1 1343 H_GT_VSS_SENSE
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1072 RPR137 100.00 100.00 2 R 1 1343 0 140.00 60.00 101.73 0.0000 16369233 15660831 140.00 60.000  

RPR138
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR138 F3 T 2 2 100.0  

Pin Nail Net Name
1 1342 H_GT_VCC_SENSE
2 1340 VCCGT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1073 RPR138 100.00 100.00 2 R 1340 1342 0 140.00 60.00 101.73 0.0000 16369233 15660831 140.00 60.000  

RPR139
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR139 F3 T 2 2 100.0  

Pin Nail Net Name
1 1600 P_GT_VSNA_10
2 1343 H_GT_VSS_SENSE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1186 RPR139 1.500K 1.500K 2 R 1343 1600 0 1.650K 1.350K 1.510K 0.0006 85.627 78.991 1.6500 1.3500  

RPR140
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR140 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1620 P_GT_TMA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1124 RPR140 680.00 680.00 2 R 1 1620 1656 952.00 408.00 686.13 1.1936 75.960 74.247 952.00 408.00  

RPR141
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR141 F3 T 2 2 100.0  

Pin Nail Net Name
1 1623 P_VCORE_TM_10
2 1674 P_VCORE_TM_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1078 RPR141 205.00 205.00 2 R 1623 1674 0 287.00 123.00 203.89 0.0000 7655724 7552419 287.00 123.00  

RPR146
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR146 F3 T 2 2 100.0  

Pin Nail Net Name
1 1612 P_GT_DIFFA_10
2 1599 P_GT_FBA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1180 RPR146 1.000K 1.000K 2 R 1599 1612 0 1.100K 0.900K 1.000K 0.0000 9696396 9682673 1.1000 0.9000  

RPR147
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR147 F3 T 2 2 100.0  

Pin Nail Net Name
1 1612 P_GT_DIFFA_10
2 1598 P_GT_DIFFA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1058 RPR147 49.90 49.90 2 R 1598 1612 0 69.86 29.94 50.91 0.0224 297.59 282.48 69.860 29.940  

RPR148
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR148 F3 T 2 2 100.0  

Pin Nail Net Name
1 1599 P_GT_FBA_10
2 1615 P_GT_FBA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1268 RPR148 6.650K 6.650K 2 R 1599 1615 0 7.315K 5.985K 6.650K 0.0000 5056097 5030812 7.3200 5.9900  

RPR149
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR149 F3 T 2 2 100.0  

Pin Nail Net Name
1 1638 P_GT_BOOT_R
2 1664 P_GT_PWM2A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1421 RPR149 10.00K 10.00K 2 R 1638 1664 0 11.00K 9.00K 10.08K 0.0000 2366195 2176053 11.000 9.0000  

RPR150
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR150 F3 T 2 2 100.0  

Pin Nail Net Name
1 1637 P_VCORE_BOOT_R
2 1684 P_VCORE_PWM2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1408 RPR150 10.00K 10.00K 2 R 1637 1684 0 11.00K 9.00K 10.08K 0.0000 2366195 2176053 11.000 9.0000  

RPR153
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR153 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1622 P_VCORE_SM_ADDR_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1423 RPR153 10.00K 10.00K 2 R 1594 1622 0 11.00K 9.00K 9.64K 0.0000 3622878 2320503 11.000 9.0000  

RPR154
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR154 F3 T 2 2 100.0  

Pin Nail Net Name
1 1628 P_VCORE_FB_10
2 1631 P_VCORE_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1269 RPR154 6.650K 6.650K 2 R 1628 1631 0 7.315K 5.985K 6.690K 0.0038 58.772 55.433 7.3200 5.9900  

RPR155
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR155 F3 T 2 2 100.0  

Pin Nail Net Name
1 1604 P_VCORE_DIFF_10
2 1628 P_VCORE_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1128 RPR155 1.000K 1.000K 2 R 1628 1604 0 1.100K 0.900K 1.000K 0.0003 129.18 123.43 1.1000 0.9000  

RPR156
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR156 F3 T 2 2 100.0  

Pin Nail Net Name
1 1604 P_VCORE_DIFF_10
2 1627 P_VCORE_DIFF_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1054 RPR156 49.90 49.90 2 R 1627 1604 0 69.86 29.94 51.37 0.0394 168.85 156.43 69.860 29.940  

RPR157
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR157 F2 T 2 2 100.0 Parallel QPQ111_3_4

Pin Nail Net Name
1 1320 P_VCORE_PHASE1_20
2 1693 P_VCORE_R_HG1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1319 RPR157/Q 8.200K 8.200K 2 R 1320 1693 1 9.020K 6.560K 7.450K 0.0000 3742102 2705013 9.0200 6.5600  

RPR158
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR158 E2 T 2 2 100.0 Parallel QPQ121_3_4

Pin Nail Net Name
1 1319 P_VCORE_PHASE2_20
2 1313 P_VCORE_R_HG2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1320 RPR158/Q 8.200K 8.200K 2 R 1319 1313 1 9.020K 6.560K 7.050K 0.0042 97.946 38.856 9.0200 6.5600  

RPR159
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR159 E2 T 2 2 100.0 Parallel QPQ131_3_4

Pin Nail Net Name
1 1199 P_VCORE_PHASE3_20
2 1317 P_VCORE_R_HG3_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1321 RPR159/Q 8.200K 8.200K 2 R 1199 1317 1 9.020K 6.560K 7.030K 0.0000 3656450 1393202 9.0200 6.5600  

RPR163
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR163 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1685 P_VCORE_PWM3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1496 RPR163 133.00K 133.00K 2 R 1594 1685 0 146.30K 119.70K 132.49K 0.0000 3970056 3818378 146.30 119.70  

RPR164
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR164 F2 T 2 2 100.0  

Pin Nail Net Name
1 1681 P_VCORE_DRON_10
2 1679 P_OD_2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1055 RPR164 49.90 49.90 2 R 1681 1679 0 69.86 29.94 50.82 0.0000 6682030 6373029 69.860 29.940  

RPR168
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR168 F2 T 2 2 100.0  

Pin Nail Net Name
1 1681 P_VCORE_DRON_10
2 1689 P_OD_3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1056 RPR168 49.90 49.90 2 R 1681 1689 0 69.86 29.94 50.99 0.0224 296.69 280.48 69.860 29.940  

RPR169
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR169 F2 T 2 2 100.0  

Pin Nail Net Name
1 1681 P_VCORE_DRON_10
2 1680 P_OD_1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1057 RPR169 49.90 49.90 2 R 1681 1680 0 69.86 29.94 51.02 0.0000 17122404 16164503 69.860 29.940  

RPR186
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR186 F3 T 2 2 100.0  

Pin Nail Net Name
1 1330 H_SVID_CLK
2 1601 P_SVID_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1059 RPR186 49.90 49.90 2 R 1330 1601 0 69.86 29.94 51.81 0.0000 7657371 6926180 69.860 29.940  

RPR187
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR187 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1550 P_VRM_PGD_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1219 RPR187 2.700K 2.700K 2 R 1594 1550 3 2.970K 2.430K 2.720K 0.0000 3403885 3094365 2.9700 2.4300  

RPR189
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR189 F3 T 2 2 100.0  

Pin Nail Net Name
1 1550 P_VRM_PGD_10
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1323 RPR189 8.200K 8.200K 2 R 3 1550 1 9.020K 7.380K 8.280K 0.0058 47.269 42.617 9.0200 7.3800  

RPR195
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR195 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1683 P_VCORE_PWM1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1431 RPR195 10.00K 10.00K 2 R 1594 1683 0 11.00K 9.00K 10.07K 0.0000 7908855 7390479 11.000 9.0000  

RPR197
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR197 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1637 P_VCORE_BOOT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1479 RPR197 49.90K 49.90K 2 R 1594 1637 0 54.89K 44.91K 50.31K 0.0000 1929440 1770302 54.890 44.910  

RPR198
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR198 F3 T 2 2 100.0  

Pin Nail Net Name
1 1594 DGND
2 1638 P_GT_BOOT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1478 RPR198 49.90K 49.90K 2 R 1594 1638 0 54.89K 44.91K 50.53K 0.0373 44.616 38.944 54.890 44.910  

RPR199
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR199 F3 T 2 2 100.0  

Pin Nail Net Name
1 1633 P_VCORE_CSP4_10
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1324 RPR199 8.200K 8.200K 2 R 3 1633 0 9.020K 7.380K 7.800K 0.0051 53.278 27.466 9.0200 7.3800  

RPR201
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR201 F2 T 2 2 100.0 Parallel QPQ211_3_4

Pin Nail Net Name
1 1657 P_GT_PHASE1_20
2 1655 P_GT_R_HG1_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1322 RPR201/Q 8.200K 8.200K 2 R 1657 1655 1 9.020K 6.560K 7.850K 0.0000 8568045 8147173 9.0200 6.5600  

RPR202
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR202 F2 T 2 2 100.0  

Pin Nail Net Name
1 1671 P_GT_PHASE2_20
2 1668 P_GT_R_HG2_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1325 RPR202 8.200K 8.200K 2 R 1671 1668 1316 9.020K 7.380K 7.980K 0.0054 50.879 37.517 9.0200 7.3800  

RPR207
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR207 F3 T 2 2 100.0  

Pin Nail Net Name
1 1681 P_VCORE_DRON_10
2 1649 P_GT_OD_1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1052 RPR207 49.90 49.90 2 R 1681 1649 0 69.86 29.94 51.38 0.0228 292.24 270.54 69.860 29.940  

RPR210
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR210 F2 T 2 2 100.0  

Pin Nail Net Name
1 1681 P_VCORE_DRON_10
2 1665 P_GT_OD_2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1053 RPR210 49.90 49.90 2 R 1681 1665 0 69.86 29.94 51.09 0.0000 8581734 8068160 69.860 29.940  

RPR224
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR224 F3 T 2 2 100.0  

Pin Nail Net Name
1 1592 P_GT_IOUTA_10
2 1611 P_GT_IOUTA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1090 RPR224 300.00 300.00 2 R 1611 1592 0 420.00 180.00 304.68 0.0000 9464164 9094856 420.00 180.00  

RPR225
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR225 F3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 1225 P_VCORE_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1156 RPR225 1.000K 1.000K 2 R 2 1225 0 1.100K 0.900K 1.000K 0.0014 24.515 23.860 1.1000 0.9000  

RPR307
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR307 D4 T 2 2 100.0  

Pin Nail Net Name
1 1203 P_+VCCIO_EN_10
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1158 RPR307 1.000K 1.000K 2 R 2 1203 0 1.100K 0.900K 1.000K 0.0000 2602580 2560088 1.1000 0.9000  

RPR323
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR323 B4 T 2 2 100.0  

Pin Nail Net Name
1 432 P_VCCIO_PG_G2_10
2 423 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1326 RPR323 8.200K 8.200K 2 R 423 432 0 9.020K 7.380K 8.190K 0.0057 48.303 47.806 9.0200 7.3800  

RPR328
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR328 C4 T 2 2 100.0  

Pin Nail Net Name
1 923 P_VCCIO_PG_G1_10
2 878 VCCIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1327 RPR328 8.200K 8.200K 2 R 878 923 0 9.020K 7.380K 8.240K 0.0057 47.727 45.157 9.0200 7.3800  

RPR407
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR407 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 611 P_3V_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1185 RPR407 1.500K 1.500K 2 R 1 611 5 1.650K 1.350K 1.510K 0.0012 43.186 41.676 1.6500 1.3500  

RPR413
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR413 B2 T 2 2 100.0  

Pin Nail Net Name
1 628 P_+3V_OV_ER_10
2 626 P_+3V_OV_E_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1116 RPR413 499.00 499.00 2 R 626 628 706 698.60 299.40 501.31 0.2123 313.45 309.83 698.60 299.40  

RPR415
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR415 B2 T 2 2 100.0  

Pin Nail Net Name
1 608 P_+3V_OV_REF_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1328 RPR415 8.200K 8.200K 2 R 1 608 2 9.020K 7.380K 8.290K 0.0058 47.154 41.745 9.0200 7.3800  

RPR416
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR416 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 626 P_+3V_OV_E_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1329 RPR416 8.200K 8.200K 2 R 1 626 628 9.020K 7.380K 8.240K 0.0000 1802483 1719964 9.0200 7.3800  

RPR418
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR418 B2 T 2 2 100.0  

Pin Nail Net Name
1 706 +3VSB_ATX
2 628 P_+3V_OV_ER_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1117 RPR418 499.00 499.00 2 R 706 628 0 698.60 299.40 475.61 0.0000 12885841 11375588 698.60 299.40  

RPR421
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR421 B2 T 2 2 100.0  

Pin Nail Net Name
1 611 P_3V_GATE_10
2 5 -12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1419 RPR421 10.00K 10.00K 2 R 5 611 1 11.00K 9.00K 10.20K 0.0264 12.649 10.113 11.000 9.0000  

RPR426
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR426 B2 T 2 2 100.0  

Pin Nail Net Name
1 609 P_+3V_OV_G_10
2 164 +3V_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1330 RPR426 8.200K 8.200K 2 R 164 609 0 9.020K 7.380K 8.240K 0.0057 47.727 45.350 9.0200 7.3800  

RPR429
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR429 B2 T 2 2 100.0  

Pin Nail Net Name
1 609 P_+3V_OV_G_10
2 610 P_+3V_OV_G1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1331 RPR429 8.200K 8.200K 2 R 609 610 0 9.020K 7.380K 8.250K 0.0000 3746707 3529858 9.0200 7.3800  

RPR431
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR431 B2 T 2 2 100.0  

Pin Nail Net Name
1 608 P_+3V_OV_REF_10
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1155 RPR431 1.000K 1.000K 2 R 2 608 1 1.100K 0.900K 1.010K 0.0000 2858741 2645975 1.1000 0.9000  

RPR508
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR508 F4 T 2 2 100.0  

Pin Nail Net Name
1 675 S_SLP_S4_
2 1504 P_SLP_S4__R1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1406 RPR508 10.00K 10.00K 2 R 675 1504 0 11.00K 9.00K 10.11K 0.0086 38.744 34.670 11.000 9.0000  

RPR531
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR531 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1499 P_VDDQ_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1125 RPR531 732.00 732.00 2 R 1 1499 1502 1024.80 439.20 791.48 1.9085 51.140 40.751 1024.8 439.20  

RPR533
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR533 F4 T 2 2 100.0  

Pin Nail Net Name
1 1499 P_VDDQ_FB_10
2 1502 P_VDDQ_FB_SHORTPIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1118 RPR533 499.00 499.00 2 R 1502 1499 1 698.60 299.40 530.49 0.2377 279.95 235.79 698.60 299.40  

RPR535
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR535 E4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1492 P_VDDQ_LGATE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1446 RPR535 13.30K 13.30K 2 R 1 1492 0 14.63K 11.97K 13.37K 0.0046 97.020 91.633 14.630 11.970  

RPR537
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR537 F4 T 2 2 100.0  

Pin Nail Net Name
1 1507 P_VDDQ_COMP_10
2 1500 P_VDDQ_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1464 RPR537 32.40K 32.40K 2 R 1507 1500 0 35.64K 29.16K 32.75K 0.0547 19.728 17.582 35.640 29.160  

RPR540
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR540 F4 T 2 2 100.0  

Pin Nail Net Name
1 1510 P_VDDQ_REFOUT_10
2 1509 P_VDDQ_OFS_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1081 RPR540 255.00 255.00 2 R 1509 1510 0 357.00 153.00 257.32 0.0000 28309734 27666760 357.00 153.00  

RPR542
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR542 C4 T 2 2 100.0  

Pin Nail Net Name
1 903 P_VTT_DDR_REFIN_10
2 1108 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1412 RPR542 10.00K 10.00K 2 R 1108 903 1 11.00K 9.00K 10.32K 0.0156 21.422 14.493 11.000 9.0000  

RPR545
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR545 C4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 903 P_VTT_DDR_REFIN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1413 RPR545 10.00K 10.00K 2 R 1 903 1108 11.00K 9.00K 10.58K 0.0094 35.282 14.677 11.000 9.0000  

RPR546
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR546 C4 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 910 P_VTT_DDR_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1332 RPR546 8.200K 8.200K 2 R 2 910 0 9.020K 7.380K 8.210K 0.0057 48.072 47.223 9.0200 7.3800  

RPR550
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR550 F4 T 2 2 100.0  

Pin Nail Net Name
1 671 O_3VSBSW_
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1135 RPR550 1.000K 1.000K 2 R 970 671 0 1.100K 0.900K 1.000K 0.0003 129.07 122.74 1.1000 0.9000  

RPR551
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR551 E4 T 2 2 100.0  

Pin Nail Net Name
1 970 +5VSB_ATX
2 1487 P_+VDDQ_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1333 RPR551 8.200K 8.200K 2 R 970 1487 0 9.020K 7.380K 8.230K 0.0057 47.842 46.037 9.0200 7.3800  

RPR552
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR552 E4 T 2 2 100.0  

Pin Nail Net Name
1 1488 P_+VDDQ_S
2 1108 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1062 RPR552 51.00 51.00 2 R 1108 1488 0 71.40 30.60 52.30 0.0236 288.35 269.90 71.400 30.600  

RPR553
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR553 D4 T 2 2 100.0  

Pin Nail Net Name
1 972 P_+VDDQ_PG1_10
2 1108 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1160 RPR553 1.000K 1.000K 2 R 1108 972 0 1.100K 0.900K 1.000K 0.0000 3277550 3194885 1.1000 0.9000  

RPR554
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR554 D4 T 2 2 100.0  

Pin Nail Net Name
1 972 P_+VDDQ_PG1_10
2 979 P_+VDDQ_PG_B1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1416 RPR554 10.00K 10.00K 2 R 979 972 0 11.00K 9.00K 9.45K 0.0528 6.3110 2.8130 11.000 9.0000  

RPR556
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR556 D4 T 2 2 100.0  

Pin Nail Net Name
1 978 P_+VDDQ_PG_B2_10
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1420 RPR556 10.00K 10.00K 2 R 970 978 0 11.00K 9.00K 10.07K 0.0000 7908855 7390479 11.000 9.0000  

RPR559
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR559 F4 T 2 2 100.0  

Pin Nail Net Name
1 1508 P_VDDQ_COMP_GATE_10
2 671 O_3VSBSW_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1474 RPR559 40.20K 40.20K 2 R 1508 671 0 44.22K 36.18K 37.72K 0.0937 14.305 5.4670 44.220 36.180  

RPR560
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR560 F4 T 2 2 100.0  

Pin Nail Net Name
1 1506 P_+5V_R1_10
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1476 RPR560 40.20K 40.20K 2 R 3 1506 1 44.22K 36.18K 40.92K 0.0141 94.948 78.053 44.220 36.180  

RPR565
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR565 C4 T 2 2 100.0  

Pin Nail Net Name
1 924 DDR_VTT_CNTL_B_R_10
2 922 DDR_VTT_CNTL_B_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1168 RPR565 1.000K 1.000K 2 R 922 924 0 1.100K 0.900K 1.000K 0.0000 3277550 3194885 1.1000 0.9000  

RPR567
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR567 C4 T 2 2 100.0  

Pin Nail Net Name
1 920 P_DDR_VTT_C_10
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1334 RPR567 8.200K 8.200K 2 R 970 920 0 9.020K 7.380K 8.120K 0.0000 4711689 4253970 9.0200 7.3800  

RPR568
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR568 F4 T 2 2 100.0  

Pin Nail Net Name
1 1506 P_+5V_R1_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1445 RPR568 13.00K 13.00K 2 R 1 1506 3 14.30K 11.70K 13.06K 0.0000 2346232 2234128 14.300 11.700  

RPR599
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR599 F4 T 2 2 100.0 Parallel QPQ511_3_4

Pin Nail Net Name
1 1490 P_VDDQ_PHASE_20
2 1493 P_VDDQ_UGATE_M_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1335 RPR599/Q 8.200K 5.000K 2 R 1490 1493 1 6.500K 3.500K 5.450K 0.0025 200.08 140.68 6.5000 3.5000  

RPR601
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR601 B4 T 2 2 100.0  

Pin Nail Net Name
1 394 P_+5VSB_ATX_OV_E_10
2 402 P_+5VSB_ATX_OV_E_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1115 RPR601 499.00 499.00 2 R 394 402 0 698.60 299.40 475.50 0.3822 174.06 153.56 698.60 299.40  

RPR603
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR603 B4 T 2 2 100.0  

Pin Nail Net Name
1 393 P_+5VSB_ATX_OV_REF_10
2 423 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1233 RPR603 2.940K 2.940K 2 R 423 393 1 3.234K 2.646K 2.960K 0.0000 2140807 2022477 3.2300 2.6500  

RPR604
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR604 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 393 P_+5VSB_ATX_OV_REF_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1254 RPR604 4.700K 4.700K 2 R 1 393 423 5.170K 4.230K 4.740K 0.0000 5947459 5380216 5.1700 4.2300  

RPR605
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR605 B4 T 2 2 100.0  

Pin Nail Net Name
1 402 P_+5VSB_ATX_OV_E_R_10
2 706 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1109 RPR605 499.00 499.00 2 R 706 402 394 698.60 299.40 502.17 0.3690 180.31 177.45 698.60 299.40  

RPR606
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR606 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 394 P_+5VSB_ATX_OV_E_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1337 RPR606 8.200K 8.200K 2 R 1 394 402 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RPR607
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR607 C4 T 2 2 100.0  

Pin Nail Net Name
1 952 P_+5VSB_ATX_OV_G_10
2 947 P_+5VSB_ATX_OV_B_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1409 RPR607 10.00K 10.00K 2 R 952 947 0 11.00K 9.00K 10.04K 0.0000 2217642 2137705 11.000 9.0000  

RPR608
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR608 B4 T 2 2 100.0  

Pin Nail Net Name
1 952 P_+5VSB_ATX_OV_G_10
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1438 RPR608 10.00K 10.00K 2 R 970 952 0 11.00K 9.00K 10.05K 0.0000 2881908 2735584 11.000 9.0000  

RPR609
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR609 B4 T 2 2 100.0  

Pin Nail Net Name
1 970 +5VSB_ATX
2 405 P_5VSB_SHORT_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1102 RPR609 470.00 470.00 2 R 970 405 0 658.00 282.00 471.67 0.0000 8396213 8321771 658.00 282.00  

RPR610
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR610 B4 T 2 2 100.0  

Pin Nail Net Name
1 412 P_5VSB_GATE_10_1
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1338 RPR610 8.200K 8.200K 2 R 970 412 408 9.020K 7.380K 8.350K 0.0000 19609588 16070678 9.0200 7.3800  

RPR611
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR611 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 400 P_5VSB_Q3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1240 RPR611 4.700K 4.700K 2 R 1 400 401 5.170K 4.230K 4.740K 0.0000 3322136 3028506 5.1700 4.2300  

RPR612
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR612 C4 T 2 2 100.0  

Pin Nail Net Name
1 404 P_5VSB_GATE1_10
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1470 RPR612 40.20K 40.20K 2 R 4 404 0 44.22K 36.18K 40.57K 0.0240 55.772 50.667 44.220 36.180  

RPR613
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR613 B4 T 2 2 100.0  

Pin Nail Net Name
1 400 P_5VSB_Q3_10
2 401 P_5VSB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1339 RPR613 8.200K 8.200K 2 R 401 400 1 9.020K 7.380K 8.260K 0.0000 2788191 2593008 9.0200 7.3800  

RPR614
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR614 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 406 P_5VSB_Q2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1241 RPR614 4.700K 4.700K 2 R 1 406 401 5.170K 4.230K 4.710K 0.0019 83.863 82.653 5.1700 4.2300  

RPR615
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR615 B4 T 2 2 100.0  

Pin Nail Net Name
1 406 P_5VSB_Q2_10
2 401 P_5VSB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1340 RPR615 8.200K 8.200K 2 R 401 406 1 9.020K 7.380K 8.210K 0.0057 48.072 47.415 9.0200 7.3800  

RPR616
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR616 B4 T 2 2 100.0  

Pin Nail Net Name
1 401 P_5VSB_Q1_10
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1243 RPR616 4.700K 4.700K 2 R 970 401 1 5.170K 4.230K 4.720K 0.0000 4070357 3908651 5.1700 4.2300  

RPR617
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR617 D4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 980 P_5V_USB_Q2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1244 RPR617 4.700K 4.700K 2 R 1 980 971 5.170K 4.230K 4.720K 0.0000 5846033 5654196 5.1700 4.2300  

RPR618
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR618 D4 T 2 2 100.0  

Pin Nail Net Name
1 971 P_5V_USB_Q1_10
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1245 RPR618 4.700K 4.700K 2 R 970 971 1 5.170K 4.230K 4.720K 0.0000 4070357 3908651 5.1700 4.2300  

RPR619
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR619 D4 T 2 2 100.0  

Pin Nail Net Name
1 362 P_5VSB_USB_GATE_10_1
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1341 RPR619 8.200K 8.200K 2 R 970 362 0 9.020K 7.380K 8.200K 0.0000 2568546 2562593 9.0200 7.3800  

RPR620
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR620 E4 T 2 2 100.0  

Pin Nail Net Name
1 970 +5VSB_ATX
2 1486 P_5VSB_DUAL_SHORT_10_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1095 RPR620 470.00 470.00 2 R 970 1486 0 658.00 282.00 468.43 0.0000 7471777 7409513 658.00 282.00  

RPR621
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR621 D4 T 2 2 100.0  

Pin Nail Net Name
1 981 P_5V_USB_Q3_10
2 971 P_5V_USB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1342 RPR621 8.200K 8.200K 2 R 971 981 1 9.020K 7.380K 8.170K 0.0056 48.650 46.605 9.0200 7.3800  

RPR622
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR622 D4 T 2 2 100.0  

Pin Nail Net Name
1 1489 P_5V_USB_GATE_10
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1475 RPR622 40.20K 40.20K 2 R 4 1489 0 44.22K 36.18K 40.20K 0.0136 98.382 98.260 44.220 36.180  

RPR623
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR623 D4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 981 P_5V_USB_Q3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1246 RPR623 4.700K 4.700K 2 R 1 981 971 5.170K 4.230K 4.620K 0.0000 5722945 4710773 5.1700 4.2300  

RPR624
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR624 D4 T 2 2 100.0  

Pin Nail Net Name
1 980 P_5V_USB_Q2_10
2 971 P_5V_USB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1343 RPR624 8.200K 8.200K 2 R 971 980 1 9.020K 7.380K 8.250K 0.0057 47.612 44.472 9.0200 7.3800  

RPR625
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR625 B4 T 2 2 100.0  

Pin Nail Net Name
1 403 P_5VSB_B1_10
2 772 O_PWROK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1344 RPR625 8.200K 8.200K 2 R 772 403 0 9.020K 7.380K 8.210K 0.0000 2423629 2400208 9.0200 7.3800  

RPR626
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR626 D4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 974 P_+5VSB_DUAL_OV_E_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1345 RPR626 8.200K 8.200K 2 R 1 974 976 9.020K 7.380K 8.210K 0.0057 48.072 47.415 9.0200 7.3800  

RPR627
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR627 B4 T 2 2 100.0  

Pin Nail Net Name
1 408 P_5VSB_GATE_R_10
2 946 P_5VSB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1146 RPR627 1.000K 1.000K 2 R 946 408 0 1.100K 0.900K 0.970K 0.0008 40.079 27.640 1.1000 0.9000  

RPR628
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR628 B4 T 2 2 100.0  

Pin Nail Net Name
1 412 P_5VSB_GATE_10_1
2 408 P_5VSB_GATE_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1147 RPR628 1.000K 1.000K 2 R 412 408 0 1.100K 0.900K 0.960K 0.0002 140.81 87.417 1.1000 0.9000  

RPR630
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR630 B4 T 2 2 100.0  

Pin Nail Net Name
1 409 P_5VSB_GATE_RC_10
2 410 P_5VSB_GATE_B1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1157 RPR630 1.000K 1.000K 2 R 409 410 0 1.100K 0.900K 1.000K 0.0000 9203032 9134488 1.1000 0.9000  

RPR631
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR631 B4 T 2 2 100.0  

Pin Nail Net Name
1 413 P_5VSB_GATE_D_10
2 409 P_5VSB_GATE_RC_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1490 RPR631 100.00K 100.00K 2 R 409 413 0 110.00K 90.00K 101.08K 0.2866 11.630 10.377 110.00 90.000  

RPR632
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR632 B4 T 2 2 100.0  

Pin Nail Net Name
1 411 P_SLPS3__C1_10
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1346 RPR632 8.200K 8.200K 2 R 3 411 1 9.020K 7.380K 8.270K 0.0000 9394368 8622538 9.0200 7.3800  

RPR633
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR633 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 411 P_SLPS3__C1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1347 RPR633 8.200K 8.200K 2 R 1 411 3 9.020K 7.380K 8.250K 0.0000 3746707 3529858 9.0200 7.3800  

RPR634
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR634 B4 T 2 2 100.0  

Pin Nail Net Name
1 407 P_SLPS3__R_10
2 1518 S_SLP_S3_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1348 RPR634 8.200K 8.200K 2 R 1518 407 0 9.020K 7.380K 8.210K 0.0000 2423629 2400208 9.0200 7.3800  

RPR635
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR635 D4 T 2 2 100.0  

Pin Nail Net Name
1 975 P_+5VSB_DUAL_OV_G_10
2 973 P_+5VSB_DUAL_OV_B_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1418 RPR635 10.00K 10.00K 2 R 975 973 0 11.00K 9.00K 10.06K 0.0085 39.088 36.911 11.000 9.0000  

RPR636
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR636 D4 T 2 2 100.0  

Pin Nail Net Name
1 974 P_+5VSB_DUAL_OV_E_10
2 976 P_+5VSB_DUAL_OV_E_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1106 RPR636 499.00 499.00 2 R 974 976 0 698.60 299.40 475.06 0.1907 348.85 307.00 698.60 299.40  

RPR637
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR637 D4 T 2 2 100.0  

Pin Nail Net Name
1 976 P_+5VSB_DUAL_OV_E_R_10
2 706 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1107 RPR637 499.00 499.00 2 R 706 976 974 698.60 299.40 501.92 0.2129 312.54 307.96 698.60 299.40  

RPR639
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR639 D4 T 2 2 100.0  

Pin Nail Net Name
1 975 P_+5VSB_DUAL_OV_G_10
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1434 RPR639 10.00K 10.00K 2 R 970 975 0 11.00K 9.00K 10.08K 0.0000 2366195 2176053 11.000 9.0000  

RPR640
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR640 D4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 977 P_+5VSB_DUAL_OV_REF_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1239 RPR640 4.700K 4.700K 2 R 1 977 1229 5.170K 4.230K 4.580K 0.0018 88.775 65.305 5.1700 4.2300  

RPR641
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR641 D4 T 2 2 100.0  

Pin Nail Net Name
1 977 P_+5VSB_DUAL_OV_REF_10
2 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1232 RPR641 2.940K 2.940K 2 R 1229 977 1 3.234K 2.646K 2.980K 0.0000 1933125 1698283 3.2300 2.6500  

RPR701
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR701 A1 T 2 2 100.0  

Pin Nail Net Name
1 81 P_+3VSB_ATX_ADJ_20
2 706 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1183 RPR701 1.270K 1.270K 2 R 706 81 1 1.397K 1.143K 1.280K 0.0000 2828539 2545747 1.4000 1.1400  

RPR702
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR702 B4 T 2 2 100.0  

Pin Nail Net Name
1 435 P_+1_0V_A_FB_R_10
2 428 P_+1_0V_A_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1267 RPR702 6.040K 6.040K 2 R 428 435 436 6.644K 5.436K 6.180K 0.0032 62.611 48.593 6.6400 5.4400  

RPR707
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR707 B4 T 2 2 100.0  

Pin Nail Net Name
1 435 P_+1_0V_A_FB_R_10
2 436 P_+1_0V_A_VOUT_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1108 RPR707 499.00 499.00 2 R 436 435 0 698.60 299.40 487.60 0.2009 331.15 312.23 698.60 299.40  

RPR708
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR708 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 428 P_+1_0V_A_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1433 RPR708 10.00K 10.00K 2 R 1 428 435 11.00K 9.00K 9.98K 0.0000 4789673 4682221 11.000 9.0000  

RPR710
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR710 B4 T 2 2 100.0  

Pin Nail Net Name
1 437 P_+1_0V_A_OV1_10
2 435 P_+1_0V_A_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1405 RPR710 9.100K 9.100K 2 R 435 437 0 10.010K 8.190K 9.150K 0.0000 9019474 8513471 10.010 8.1900  

RPR712
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR712 B4 T 2 2 100.0  

Pin Nail Net Name
1 438 P_+1_0V_A_OV2_10
2 435 P_+1_0V_A_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1238 RPR712 4.700K 4.700K 2 R 435 438 0 5.170K 4.230K 4.720K 0.0019 83.518 80.585 5.1700 4.2300  

RPR713
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR713 A4 T 2 2 100.0  

Pin Nail Net Name
1 430 P_+1_0V_A_EN_10
2 423 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1432 RPR713 10.00K 10.00K 2 R 423 430 1 11.00K 9.00K 10.46K 0.0647 5.1550 2.7820 11.000 9.0000  

RPR717
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR717 A4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 430 P_+1_0V_A_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1415 RPR717 10.00K 10.00K 2 R 1 430 423 11.00K 9.00K 9.33K 0.0220 15.178 4.9410 11.000 9.0000  

RPR718
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR718 A1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 81 P_+3VSB_ATX_ADJ_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1190 RPR718 2.150K 2.150K 2 R 1 81 706 2.365K 1.935K 2.170K 0.0012 59.508 53.823 2.3700 1.9400  

RPR739
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR739 B4 T 2 2 100.0  

Pin Nail Net Name
1 429 P_+1_0V_A_FBR_10
2 433 P_+1_0V_A_SW_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1501 RPR739 1.000M 1.000M 2 R 429 433 428 1.300M 0.700M 1.060M 0.4067 0.2460 0.2000 1.3000 0.7000  

RPR740
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR740 B4 T 2 2 100.0  

Pin Nail Net Name
1 428 P_+1_0V_A_FB_10
2 429 P_+1_0V_A_FBR_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1110 RPR740 499.00 499.00 2 R 428 429 0 698.60 299.40 501.80 0.0000 11493632 11332429 698.60 299.40  

RPR741
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR741 B4 T 2 2 100.0  

Pin Nail Net Name
1 675 S_SLP_S4_
2 446 P_VCCST_VCCSFR_B_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1422 RPR741 10.00K 10.00K 2 R 675 446 0 11.00K 9.00K 10.11K 0.0000 7589466 6753737 11.000 9.0000  

RPR742
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR742 C4 T 2 2 100.0  

Pin Nail Net Name
1 921 P_VDDQ_B1_10
2 1108 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1127 RPR742 1.000K 1.000K 2 R 1108 921 0 1.100K 0.900K 1.000K 0.0000 2036513 1939722 1.1000 0.9000  

RPR743
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR743 B4 T 2 2 100.0  

Pin Nail Net Name
1 970 +5VSB_ATX
2 444 P_VCCST_VCCSFR_D1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1349 RPR743 8.200K 8.200K 2 R 970 444 0 9.020K 7.380K 8.170K 0.0113 24.296 23.275 9.0200 7.3800  

RPR744
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR744 B4 T 2 2 100.0  

Pin Nail Net Name
1 970 +5VSB_ATX
2 445 P_VCCST_VCCSFR_C_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1473 RPR744 40.20K 40.20K 2 R 970 445 0 44.22K 36.18K 40.66K 0.0000 4779506 4227484 44.220 36.180  

RPR747
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR747 C4 T 2 2 100.0  

Pin Nail Net Name
1 911 P_VDDQ_G1_10
2 423 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1350 RPR747 8.200K 8.200K 2 R 423 911 0 9.020K 7.380K 8.220K 0.0057 47.957 46.725 9.0200 7.3800  

RPR750
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR750 B4 T 2 2 100.0  

Pin Nail Net Name
1 388 P_OV1_ADD_10
2 422 +5VDUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1435 RPR750 10.00K 10.00K 2 R 422 388 0 11.00K 9.00K 10.08K 0.0086 38.973 36.034 11.000 9.0000  

RPR755
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR755 D1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1220 P_VCCSA_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1188 RPR755 1.600K 1.600K 2 R 1 1220 1218 1.760K 1.440K 1.480K 0.0006 95.787 21.397 1.7600 1.4400  

RPR756
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR756 D1 T 2 2 100.0  

Pin Nail Net Name
1 1216 P_VCCSA_REFOUT_10
2 1217 P_VCCSA_OFS_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1082 RPR756 255.00 255.00 2 R 1217 1216 0 357.00 153.00 257.32 0.0000 28309734 27666760 357.00 153.00  

RPR759
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR759 D1 T 2 2 100.0  

Pin Nail Net Name
1 1222 P_VCCSA_COMP_10
2 1219 P_VCCSA_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1465 RPR759 32.40K 32.40K 2 R 1222 1219 0 35.64K 29.16K 32.82K 0.0275 39.284 34.243 35.640 29.160  

RPR760
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR760 D2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1206 P_VCCSA_LGATE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1462 RPR760 25.50K 25.50K 2 R 1 1206 0 28.05K 22.95K 25.67K 0.0000 2602268 2426407 28.050 22.950  

RPR762
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR762 D1 T 2 2 100.0  

Pin Nail Net Name
1 1220 P_VCCSA_FB_10
2 1218 P_VCCSA_FB_SHORTPIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1111 RPR762 499.00 499.00 2 R 1218 1220 1 698.60 299.40 545.45 0.0000 16812736 12900138 698.60 299.40  

RPR764
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR764 D2 T 2 2 100.0 Parallel QPQ710_3_4

Pin Nail Net Name
1 1198 P_VCCSA_PHASE_20
2 1201 P_VCCSA_UGATE_M_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1336 RPR764/Q 8.200K 5.000K 2 R 1198 1201 1 6.500K 3.500K 4.880K 0.0020 249.57 228.85 6.5000 3.5000  

RPR767
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR767 D1 T 2 2 100.0  

Pin Nail Net Name
1 1228 P_VCCSA_C1_10
2 423 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1351 RPR767 8.200K 8.200K 2 R 423 1228 0 9.020K 7.380K 8.210K 0.0057 48.072 47.415 9.0200 7.3800  

RPR768
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR768 D1 T 2 2 100.0  

Pin Nail Net Name
1 1223 P_VCCSA_B1_10
2 1203 P_+VCCIO_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1129 RPR768 1.000K 1.000K 2 R 1203 1223 0 1.100K 0.900K 1.000K 0.0000 2602580 2560088 1.1000 0.9000  

RPR801
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR801 F3 T 2 2 100.0  

Pin Nail Net Name
1 970 +5VSB_ATX
2 1587 P_VREN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1252 RPR801 4.700K 4.700K 2 R 970 1587 0 5.170K 4.230K 4.730K 0.0000 2692288 2491886 5.1700 4.2300  

RPR802
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR802 F3 T 2 2 100.0  

Pin Nail Net Name
1 373 P_VR_READY_10
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1130 RPR802 1.000K 1.000K 2 R 2 373 0 1.100K 0.900K 1.000K 0.0003 130.22 129.64 1.1000 0.9000  

RPR803
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR803 F3 T 2 2 100.0  

Pin Nail Net Name
1 1518 S_SLP_S3_
2 1588 P_VREN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1424 RPR803 10.00K 10.00K 2 R 1518 1588 0 11.00K 9.00K 10.10K 0.0000 2066968 1870161 11.000 9.0000  

RPR805
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR805 F4 T 2 2 100.0  

Pin Nail Net Name
1 1549 P_VCORE_PG__10
2 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1352 RPR805 8.200K 8.200K 2 R 970 1549 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RPR808
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR808 F3 T 2 2 100.0  

Pin Nail Net Name
1 423 +5VSB
2 1585 P_+12V_3V_EN_C1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1471 RPR808 40.20K 40.20K 2 R 423 1585 0 44.22K 36.18K 40.67K 0.0139 96.086 84.796 44.220 36.180  

RPR809
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR809 F3 T 2 2 100.0  

Pin Nail Net Name
1 1316 +12V_CPU
2 1583 P_+12V_3V_EN_R1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1463 RPR809 27.00K 27.00K 2 R 1316 1583 1 29.70K 24.30K 25.98K 0.0172 52.196 32.423 29.700 24.300  

RPR812
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR812 F3 T 2 2 100.0  

Pin Nail Net Name
1 1583 P_+12V_3V_EN_R1_10
2 1584 P_+12V_3V_EN_B1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1428 RPR812 10.00K 10.00K 2 R 1584 1583 1 11.50K 9.00K 10.66K 0.9301 0.4480 0.3020 11.500 9.0000  

RPR814
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR814 F3 T 2 2 100.0  

Pin Nail Net Name
1 1583 P_+12V_3V_EN_R1_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1237 RPR814 3.900K 3.900K 2 R 1 1583 1316 4.290K 3.510K 4.240K 0.0015 85.629 10.107 4.2900 3.5100  

RPR815
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR815 F3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 1597 P_+12V_3V_EN_R2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1426 RPR815 10.00K 10.00K 2 R 2 1597 1 11.00K 9.00K 10.22K 0.0088 37.835 29.483 11.000 9.0000  

RPR816
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR816 F3 T 2 2 100.0  

Pin Nail Net Name
1 1597 P_+12V_3V_EN_R2_10
2 1596 P_+12V_3V_EN_B2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1439 RPR816 10.00K 10.00K 2 R 1596 1597 1 11.00K 9.00K 9.97K 0.0743 4.4850 4.3650 11.000 9.0000  

RPR817
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR817 F3 T 2 2 100.0  

Pin Nail Net Name
1 1597 P_+12V_3V_EN_R2_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1265 RPR817 5.600K 5.600K 2 R 1 1597 2 6.160K 5.040K 5.600K 0.0000 2236984 2226247 6.1600 5.0400  

RPR837
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR837 A4 T 2 2 100.0  

Pin Nail Net Name
1 344 N16717240
2 966 P_5VSB_USB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1253 RPR837 4.700K 4.700K 2 R 966 344 0 5.170K 4.230K 4.590K 0.0141 11.143 8.4400 5.1700 4.2300  

RPTR101
Device Loc Side Total Pin Tested Coverage (%) Comment
RPTR101 F2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1656 P_GT_TMA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1440 RPTR101 10.00K 10.00K 2 R 1 1656 1620 11.00K 9.00K 9.70K 0.0286 11.672 8.1670 11.000 9.0000  

RPTR102
Device Loc Side Total Pin Tested Coverage (%) Comment
RPTR102 F2 T 2 2 100.0 Parallel RPR131

Pin Nail Net Name
1 1646 P_GT_CSPA_R_10
2 1647 P_GT_CSCOMPA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1492 RPTR102/RPR13 100.00K 42.86K 2 R 1647 1646 1617 47.15K 38.57K 42.62K 0.0712 20.064 18.929 47.150 38.570  

RPTR103
Device Loc Side Total Pin Tested Coverage (%) Comment
RPTR103 E2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1674 P_VCORE_TM_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1425 RPTR103 10.00K 10.00K 2 R 1 1674 1623 11.00K 9.00K 10.14K 0.0229 14.561 12.594 11.000 9.0000  

RPTR104
Device Loc Side Total Pin Tested Coverage (%) Comment
RPTR104 E2 T 2 2 100.0 Parallel RPR136

Pin Nail Net Name
1 1322 P_VCORE_CSP_R_10
2 1323 P_VCORE_CSCOMP_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1493 RPTR104/RPR13 100.00K 37.66K 2 R 1323 1322 1635 41.43K 33.89K 37.64K 0.0708 17.729 17.649 41.430 33.890  

RSR10
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR10 B3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 526 N96817951

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1131 RSR10 1.000K 1.000K 2 R 1 526 0 1.100K 0.900K 1.000K 0.0000 2812037 2803561 1.1000 0.9000  

RSR100
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR100 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 130 S_SERIRQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1353 RSR100 8.200K 8.200K 2 R 2 130 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RSR11
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR11 B3 T 2 2 100.0  

Pin Nail Net Name
1 519 +1_0V_A_XCLK_BIAS
2 518 S_XCLK_BIASREF

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1220 RSR11 2.700K 2.700K 2 R 519 518 0 2.970K 2.430K 2.700K 0.0000 1830846 1797067 2.9700 2.4300  

RSR118
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR118 B3 T 2 2 100.0  

Pin Nail Net Name
1 545 +BAT
2 554 +BAT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1132 RSR118 1.000K 1.000K 2 R 554 545 0 1.100K 0.900K 1.010K 0.0003 128.96 121.86 1.1000 0.9000  

RSR119
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR119 A3 T 2 2 100.0  

Pin Nail Net Name
1 678 +3V_BAT
2 292 +3V_BAT_RTC

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1450 RSR119 18.70K 18.70K 2 R 678 292 1 20.57K 16.83K 19.20K 0.0000 2668415 1959405 20.570 16.830  

RSR120
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR120 A3 T 2 2 100.0  

Pin Nail Net Name
1 289 S_RTCRST_
2 292 +3V_BAT_RTC

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1133 RSR120 1.000K 1.000K 2 R 292 289 0 1.100K 0.900K 0.960K 0.0019 17.119 11.121 1.1000 0.9000  

RSR121
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR121 A3 T 2 2 100.0  

Pin Nail Net Name
1 678 +3V_BAT
2 253 S_SRTCRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1452 RSR121 20.00K 20.00K 2 R 678 253 1 22.00K 18.00K 19.43K 0.2629 2.5360 1.8140 22.000 18.000  

RSR122
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR122 A3 T 2 2 100.0  

Pin Nail Net Name
1 243 L1_LAN_WAKE_
2 179 +3VSB_ADV

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1454 RSR122 20.00K 20.00K 2 R 179 243 0 22.00K 18.00K 20.08K 0.0000 2581945 2473732 22.000 18.000  

RSR125
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR125 A3 T 2 2 100.0  

Pin Nail Net Name
1 231 CK_24M_TPM_R
2 149 CK_24M_TPM

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1012 RSR125 22.00 22.00 2 R 149 231 0 30.80 13.20 23.60 0.0000 32145906 26318690 30.800 13.200  

RSR127
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR127 A4 T 2 2 100.0  

Pin Nail Net Name
1 347 N35715912
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1354 RSR127 8.200K 8.200K 2 R 634 347 0 9.020K 7.380K 8.250K 0.0000 3746707 3529858 9.0200 7.3800  

RSR129
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR129 C2 T 2 2 100.0  

Pin Nail Net Name
1 871 S_VCCST_PWRGD
2 842 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1134 RSR129 1.000K 1.000K 2 R 842 871 0 1.100K 0.900K 1.000K 0.0003 129.53 125.49 1.1000 0.9000  

RSR131
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR131 D2 T 2 2 100.0  

Pin Nail Net Name
1 1197 S_TCC_EN_
2 1196 N28268491

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1355 RSR131 8.200K 8.200K 2 R 1196 1197 0 9.020K 7.380K 7.970K 0.0405 6.7440 4.8470 9.0200 7.3800  

RSR134
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR134 A4 T 2 2 100.0  

Pin Nail Net Name
1 634 +3VSB
2 300 S_GPP_C7

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1356 RSR134 8.200K 8.200K 2 R 634 300 0 9.020K 7.380K 8.250K 0.0000 3746707 3529858 9.0200 7.3800  

RSR135
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR135 A4 T 2 2 100.0  

Pin Nail Net Name
1 634 +3VSB
2 296 S_GPP_C6

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1357 RSR135 8.200K 8.200K 2 R 634 296 0 9.020K 7.380K 8.220K 0.0000 6629250 6485570 9.0200 7.3800  

RSR14
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR14 B3 T 2 2 100.0  

Pin Nail Net Name
1 517 S_24M_IN
2 535 S_24M_OUT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1502 RSR14 1.000M 1.000M 2 R 517 535 534 1.300M 0.700M 0.900M 0.0107 9.3730 6.0990 1.3000 0.7000  

RSR145
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR145 A3 T 2 2 100.0  

Pin Nail Net Name
1 634 +3VSB
2 258 S_GPP_A7

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1358 RSR145 8.200K 8.200K 2 R 634 258 0 9.020K 7.380K 8.220K 0.0057 47.957 46.533 9.0200 7.3800  

RSR152
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR152 B4 T 2 2 100.0  

Pin Nail Net Name
1 634 +3VSB
2 497 S_USB2_OCB_7

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1359 RSR152 8.200K 8.200K 2 R 634 497 0 9.020K 7.380K 8.220K 0.0000 6629250 6485570 9.0200 7.3800  

RSR1607
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1607 A3 T 2 2 100.0  

Pin Nail Net Name
1 210 S_RTCX2
2 209 S_RTCX1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1505 RSR1607 10.00M 10.00M 2 R 209 210 0 13.00M 7.00M 9.88M 0.0400 24.995 24.018 13.000 7.0000  

RSR1628
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1628 B3 T 2 2 100.0  

Pin Nail Net Name
1 501 +1_0V_A
2 817 S_VCORE_SHDN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1360 RSR1628 8.200K 8.200K 2 R 501 817 0 9.020K 7.380K 7.960K 0.0053 51.116 36.342 9.0200 7.3800  

RSR163
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR163 B3 T 2 2 100.0  

Pin Nail Net Name
1 546 N31918039
2 706 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1189 RSR163 2.000K 2.000K 2 R 706 546 0 2.200K 1.800K 1.930K 0.0000 2505898 1657566 2.2000 1.8000  

RSR1633
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1633 A3 T 2 2 100.0  

Pin Nail Net Name
1 634 +3VSB
2 294 S_GPP_H23

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1361 RSR1633 8.200K 8.200K 2 R 634 294 0 9.020K 7.380K 8.200K 0.0000 2568546 2562593 9.0200 7.3800  

RSR1634
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1634 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 461 GPP_G1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1362 RSR1634 8.200K 8.200K 2 R 1 461 0 9.020K 7.380K 8.250K 0.0057 47.612 44.472 9.0200 7.3800  

RSR1637
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1637 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 462 GPP_G0

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1363 RSR1637 8.200K 8.200K 2 R 1 462 0 9.020K 7.380K 8.220K 0.0000 6629250 6485570 9.0200 7.3800  

RSR1642
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1642 A4 T 2 2 100.0  

Pin Nail Net Name
1 398 +3V_SPI
2 359 F_BIOS_WP_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1143 RSR1642 1.000K 1.000K 2 R 398 359 0 1.100K 0.900K 1.000K 0.0000 9203032 9134488 1.1000 0.9000  

RSR1643
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1643 A4 T 2 2 100.0  

Pin Nail Net Name
1 398 +3V_SPI
2 397 F_SPI_HOLD_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1144 RSR1643 1.000K 1.000K 2 R 398 397 0 1.100K 0.900K 1.000K 0.0003 129.65 125.99 1.1000 0.9000  

RSR166
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR166 A4 T 2 2 100.0  

Pin Nail Net Name
1 323 L1_SMBDATA
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1113 RSR166 499.00 499.00 2 R 634 323 0 698.60 299.40 504.64 0.2151 309.33 300.59 698.60 299.40  

RSR167
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR167 A4 T 2 2 100.0  

Pin Nail Net Name
1 324 L1_SMBCLK
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1114 RSR167 499.00 499.00 2 R 634 324 0 698.60 299.40 502.29 0.2132 312.08 306.93 698.60 299.40  

RSR18
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR18 B3 T 2 2 100.0  

Pin Nail Net Name
1 516 S_PCIE_RCOMPN
2 515 S_PCIE_RCOMPP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1069 RSR18 100.00 100.00 2 R 515 516 0 140.00 60.00 101.53 0.0878 151.79 146.00 140.00 60.000  

RSR202
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR202 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 245 S_CLKRUN_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1364 RSR202 8.200K 8.200K 2 R 2 245 0 9.020K 7.380K 8.220K 0.0000 6629250 6485570 9.0200 7.3800  

RSR22
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR22 B3 T 2 2 100.0  

Pin Nail Net Name
1 525 S_USB2_COMP
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1076 RSR22 113.00 113.00 2 R 1 525 0 158.20 67.80 114.25 0.0000 23027328 22390752 158.20 67.800  

RSR242
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR242 B3 T 2 2 100.0  

Pin Nail Net Name
1 1169 S_CPU_TRIGGER
2 532 S_CPU_TRIGGER_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1027 RSR242 30.00 30.00 2 R 532 1169 0 42.00 18.00 31.97 0.0473 84.602 70.729 42.000 18.000  

RSR3
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR3 A3 T 2 2 100.0  

Pin Nail Net Name
1 222 CK_24M_SIO_R
2 46 CK_24M_SIO_IO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1014 RSR3 22.00 22.00 2 R 46 222 0 30.80 13.20 23.92 0.0000 10111642 7900931 30.800 13.200  

RSR304
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR304 A4 T 2 2 100.0  

Pin Nail Net Name
1 399 N18147149
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1148 RSR304 1.000K 1.000K 2 R 4 399 0 1.100K 0.900K 1.000K 0.0000 4893298 4864716 1.1000 0.9000  

RSR34
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR34 A4 T 2 2 100.0  

Pin Nail Net Name
1 301 S_GPP_C2
2 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1152 RSR34 1.000K 1.000K 2 R 634 301 0 1.100K 0.900K 1.000K 0.0000 3090464 3026268 1.1000 0.9000  

RSR38
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR38 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 470 S_GPP_D13

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1365 RSR38 8.200K 8.200K 2 R 1 470 0 9.020K 7.380K 8.270K 0.0000 9394368 8622538 9.0200 7.3800  

RSR4
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR4 A3 T 2 2 100.0  

Pin Nail Net Name
1 222 CK_24M_SIO_R
2 73 CK_24M_SIO_LPC

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1015 RSR4 22.00 22.00 2 R 222 73 0 30.80 13.20 24.00 0.0102 287.85 222.42 30.800 13.200  

RSR40
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR40 B3 T 2 2 100.0  

Pin Nail Net Name
1 527 S_VCORE_SHDN__10_R
2 817 S_VCORE_SHDN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1119 RSR40 560.00 560.00 2 R 817 527 0 784.00 336.00 562.35 0.2670 279.63 276.69 784.00 336.00  

RSR42
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR42 B2 T 2 2 100.0  

Pin Nail Net Name
1 607 1083_CORE_PWR_EN
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1366 RSR42 8.200K 8.200K 2 R 2 607 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RSR43
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR43 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 471 S_GPP_D14

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1367 RSR43 8.200K 8.200K 2 R 1 471 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RSR44
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR44 B3 T 2 2 100.0  

Pin Nail Net Name
1 533 S_PM_SYNC_R
2 1170 S_PM_SYNC

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1028 RSR44 30.00 30.00 2 R 1170 533 0 42.00 18.00 32.03 0.1091 36.658 30.456 42.000 18.000  

RSR49
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR49 A3 T 2 2 100.0  

Pin Nail Net Name
1 872 S_HDA_SDO_R
2 528 S_HDA_SDO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1034 RSR49 33.00 33.00 0 R 528 872 0 46.20 19.80 34.47 0.0168 262.36 233.16 46.200 19.800  

RSR5
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR5 A4 T 2 2 100.0  

Pin Nail Net Name
1 267 S_PLTRST__R
2 129 S_PLTRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1016 RSR5 22.00 22.00 2 R 129 267 0 30.80 13.20 25.57 0.0000 21165730 12576973 30.800 13.200  

RSR50
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR50 A3 T 2 2 100.0  

Pin Nail Net Name
1 870 S_HDA_SCLK
2 529 S_HDA_SCLK_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1035 RSR50 33.00 33.00 0 R 529 870 0 46.20 19.80 34.45 0.0168 262.36 233.55 46.200 19.800  

RSR52
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR52 A3 T 2 2 100.0  

Pin Nail Net Name
1 37 S_HD_BITCLK
2 241 S_HD_BITCLK_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1017 RSR52 22.00 22.00 0 R 241 37 0 30.80 13.20 24.14 0.0055 530.91 401.84 30.800 13.200  

RSR569
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR569 A3 T 2 2 100.0  

Pin Nail Net Name
1 276 S_SPI_MISO
2 358 F_SPI_MISO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1004 RSR569 15.00 15.00 0 R 358 276 0 21.00 9.00 16.38 0.0099 201.10 154.74 21.000 9.0000  

RSR57
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR57 E4 T 2 2 100.0  

Pin Nail Net Name
1 1408 S_D4_RESET__R
2 1108 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1105 RSR57 470.00 470.00 2 R 1108 1408 0 658.00 282.00 471.99 0.0000 9333830 9234899 658.00 282.00  

RSR570
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR570 A3 T 2 2 100.0  

Pin Nail Net Name
1 283 S_SPI_MOSI
2 395 F_SPI_MOSI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1005 RSR570 15.00 15.00 2 R 395 283 0 21.00 9.00 16.46 0.0049 408.22 308.70 21.000 9.0000  

RSR571
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR571 A3 T 2 2 100.0  

Pin Nail Net Name
1 295 S_SPI_CLK
2 396 F_SPI_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1006 RSR571 15.00 15.00 2 R 396 295 0 21.00 9.00 16.47 0.0000 6765011 5109362 21.000 9.0000  

RSR573
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR573 A3 T 2 2 100.0  

Pin Nail Net Name
1 281 S_SPI_IO2
2 359 F_BIOS_WP_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1007 RSR573 15.00 15.00 2 R 359 281 0 21.00 9.00 16.36 0.0000 8423642 6516024 21.000 9.0000  

RSR574
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR574 A3 T 2 2 100.0  

Pin Nail Net Name
1 279 S_SPI_IO3
2 397 F_SPI_HOLD_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1008 RSR574 15.00 15.00 2 R 397 279 0 21.00 9.00 16.47 0.0000 6765011 5109362 21.000 9.0000  

RSR60
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR60 A3 T 2 2 100.0  

Pin Nail Net Name
1 634 +3VSB
2 632 S_WAKE_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1159 RSR60 1.000K 1.000K 2 R 634 632 0 1.100K 0.900K 1.000K 0.0000 2812037 2803561 1.1000 0.9000  

RSR616
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR616 D2 T 2 2 100.0  

Pin Nail Net Name
1 1195 N28268489
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1368 RSR616 8.200K 8.200K 2 R 2 1195 0 9.020K 7.380K 8.210K 0.0057 48.072 47.223 9.0200 7.3800  

RSR701
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR701 B3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 546 N31918039

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1477 RSR701 47.00K 47.00K 2 R 1 546 706 51.70K 42.30K 46.84K 0.0000 1904672 1838625 51.700 42.300  

RSR73
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR73 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 478 S_GPP_D15

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1369 RSR73 8.200K 8.200K 2 R 1 478 0 9.020K 7.380K 8.240K 0.0057 47.727 45.157 9.0200 7.3800  

RSR75
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR75 B3 T 2 2 100.0  

Pin Nail Net Name
1 531 S_CPUPWRGD_R
2 1193 H_CPUPWRGD

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1029 RSR75 30.00 30.00 2 R 1193 531 0 42.00 18.00 31.95 0.0178 224.29 187.90 42.000 18.000  

RSR801
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR801 B3 T 2 2 100.0  

Pin Nail Net Name
1 534 S_24M_IN_R
2 517 S_24M_IN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1009 RSR801 15.00 15.00 2 R 517 534 0 21.00 9.00 16.28 0.0048 417.20 328.33 21.000 9.0000  

RSR87
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR87 B2 T 2 2 100.0  

Pin Nail Net Name
1 232 S_INTRUDER_
2 678 +3V_BAT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1499 RSR87 1.000M 1.000M 2 R 678 232 0 1.300M 0.700M 0.990M 0.0004 275.91 266.36 1.3000 0.7000  

RSR9
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR9 B3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 523 N96817948

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1161 RSR9 1.000K 1.000K 2 R 1 523 0 1.100K 0.900K 1.000K 0.0000 3090464 3026268 1.1000 0.9000  

RSR99
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR99 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 74 O_KBRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1370 RSR99 8.200K 8.200K 2 R 2 74 0 9.020K 7.380K 8.230K 0.0057 47.842 45.844 9.0200 7.3800  

RSRN202
Device Loc Side Total Pin Tested Coverage (%) Comment
RSRN202 A4 T 8 8 100.0  

Pin Nail Net Name
1 1590 S_SMBCLK_MAIN
2 2 +3V
3 1591 S_SMBDATA_MAIN
4 2 +3V
5 328 S_SMBDATA_VSB
6 634 +3VSB
7 327 S_SMBCLK_VSB
8 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1163 RSRN202_1_2 1.000K 1.000K 2 R 2 1590 0 1.100K 0.900K 0.990K 0.0000 3563582 3214758 1.1000 0.9000  
1164 RSRN202_3_4 1.000K 1.000K 2 R 2 1591 0 1.100K 0.900K 1.000K 0.0000 4709801 4599098 1.1000 0.9000  
1165 RSRN202_5_6 1.000K 1.000K 2 R 634 328 0 1.100K 0.900K 0.990K 0.0000 2743058 2522285 1.1000 0.9000  
1166 RSRN202_7_8 1.000K 1.000K 2 R 634 327 0 1.100K 0.900K 0.990K 0.0003 131.73 124.77 1.1000 0.9000  

RSRN203
Device Loc Side Total Pin Tested Coverage (%) Comment
RSRN203 A3 T 8 8 100.0  

Pin Nail Net Name
1 1301 S_HDMI_DDC_CLK
2 2 +3V
3 1242 S_HDMI_DDC_DATA
4 2 +3V
5 1253 S_DVI_DDC_DATA
6 2 +3V
7 1278 S_DVI_DDC_CLK
8 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1221 RSRN203_1_2 2.700K 2.700K 2 R 2 1301 0 2.970K 2.430K 2.720K 0.0000 3403885 3094365 2.9700 2.4300  
1222 RSRN203_3_4 2.700K 2.700K 2 R 2 1242 0 2.970K 2.430K 2.700K 0.0000 2401701 2386161 2.9700 2.4300  
1223 RSRN203_5_6 2.700K 2.700K 2 R 2 1253 0 2.970K 2.430K 2.690K 0.0000 6560131 6212453 2.9700 2.4300  
1224 RSRN203_7_8 2.700K 2.700K 2 R 2 1278 0 2.970K 2.430K 2.740K 0.0000 2959809 2545916 2.9700 2.4300  

RSRN208
Device Loc Side Total Pin Tested Coverage (%) Comment
RSRN208 B4 T 8 7 87.5 No Test Nail

Pin Nail Net Name
1 849 GP_TYPEC_PWR_CTL
2 634 +3VSB
3 467 S_GPP_C20
4 634 +3VSB
5 0 NC_2176
6 634 +3VSB
7 843 O2_PWR_EN
8 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1371 RSRN208/NP_5 8.200K 8.200K 2 R 634 0 0 9.020K 7.380K NA NA NA NA NA NA  
1372 RSRN208_1_2 8.200K 8.200K 2 R 634 849 1 9.020K 7.380K 8.150K 0.0000 1777451 1667610 9.0200 7.3800  
1373 RSRN208_3_4 8.200K 8.200K 2 R 634 467 0 9.020K 7.380K 8.060K 0.0000 4631222 3857372 9.0200 7.3800  
1374 RSRN208_7_8 8.200K 8.200K 2 R 634 843 0 9.020K 7.380K 7.510K 0.0000 3130030 481969 9.0200 7.3800  

RSRN209
Device Loc Side Total Pin Tested Coverage (%) Comment
RSRN209 A4 T 8 8 100.0  

Pin Nail Net Name
1 944 S_GPP_D21
2 634 +3VSB
3 945 S_GPP_D22
4 634 +3VSB
5 555 S_GPP_H14
6 634 +3VSB
7 943 S_GPP_H18
8 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1375 RSRN209_1_2 8.200K 8.200K 2 R 634 944 0 9.020K 7.380K 8.050K 0.0000 2001767 1644139 9.0200 7.3800  
1376 RSRN209_3_4 8.200K 8.200K 2 R 634 945 0 9.020K 7.380K 8.110K 0.0056 49.232 44.064 9.0200 7.3800  
1377 RSRN209_5_6 8.200K 8.200K 2 R 634 555 0 9.020K 7.380K 7.900K 0.0000 2722166 1711876 9.0200 7.3800  
1378 RSRN209_7_8 8.200K 8.200K 2 R 634 943 0 9.020K 7.380K 8.230K 0.0000 1829740 1768055 9.0200 7.3800  

RSRN210
Device Loc Side Total Pin Tested Coverage (%) Comment
RSRN210 A3 T 8 7 87.5 No Test Nail

Pin Nail Net Name
1 621 PCIEX1_SL1_PRSNT_
2 2 +3V
3 581 PCIEX16_SL1_PRSNT_
4 2 +3V
5 0 NC_2175
6 2 +3V
7 208 PCIEX16_SL3_PRSNT_
8 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1379 RSRN210/NP_5 8.200K 8.200K 2 R 2 0 0 9.020K 7.380K NA NA NA NA NA NA  
1380 RSRN210_1_2 8.200K 8.200K 2 R 2 621 0 9.020K 7.380K 8.240K 0.0000 1802483 1719964 9.0200 7.3800  
1381 RSRN210_3_4 8.200K 8.200K 2 R 2 581 0 9.020K 7.380K 8.090K 0.0055 49.583 42.833 9.0200 7.3800  
1382 RSRN210_7_8 8.200K 8.200K 2 R 2 208 0 9.020K 7.380K 8.120K 0.0000 4711689 4253970 9.0200 7.3800  

RSRN211
Device Loc Side Total Pin Tested Coverage (%) Comment
RSRN211 A3 T 8 8 100.0  

Pin Nail Net Name
1 266 S_GPP_A20
2 2 +3V
3 264 S_GPP_A18
4 2 +3V
5 265 S_GPP_A19
6 2 +3V
7 259 S_GPP_A17
8 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1383 RSRN211_1_2 8.200K 8.200K 2 R 2 266 0 9.020K 7.380K 8.080K 0.0000 2208748 1890936 9.0200 7.3800  
1384 RSRN211_3_4 8.200K 8.200K 2 R 2 264 0 9.020K 7.380K 8.210K 0.0057 48.072 47.223 9.0200 7.3800  
1385 RSRN211_5_6 8.200K 8.200K 2 R 2 265 0 9.020K 7.380K 8.160K 0.0000 13624904 12944239 9.0200 7.3800  
1386 RSRN211_7_8 8.200K 8.200K 2 R 2 259 0 9.020K 7.380K 8.160K 0.0000 13624904 12944239 9.0200 7.3800  

RSRN25
Device Loc Side Total Pin Tested Coverage (%) Comment
RSRN25 A3 T 8 6 75.0 No Test Nail

Pin Nail Net Name
1 0 NC_2112
2 0 NC_2113
3 40 S_HD_SDOUT
4 233 S_HD_SDOUT_R
5 42 S_HD_RST_
6 235 S_HD_RST__R
7 38 S_HD_SYNC
8 242 S_HD_SYNC_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1018 RSRN25/NP_1_ 22.00 22.00 2 R 0 0 0 30.80 17.60 NA NA NA NA NA NA  
1019 RSRN25_3_4 22.00 22.00 2 R 233 40 0 30.80 17.60 23.98 0.0102 216.20 209.07 30.800 17.600  
1020 RSRN25_5_6 22.00 22.00 2 R 235 42 0 30.80 17.60 23.89 0.0000 5715553 5446162 30.800 17.600  
1021 RSRN25_7_8 22.00 22.00 2 R 242 38 0 30.80 17.60 23.90 0.0101 217.75 207.87 30.800 17.600  

RSRN28
Device Loc Side Total Pin Tested Coverage (%) Comment
RSRN28 A3 T 8 8 100.0  

Pin Nail Net Name
1 179 +3VSB_ADV
2 246 S_GP_D0
3 179 +3VSB_ADV
4 251 S_GP_D1
5 634 +3VSB
6 249 S_SX_EXIT_HOLDOFF_
7 634 +3VSB
8 248 S_VR_ALERT_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1387 RSRN28_1_2 8.200K 8.200K 2 R 179 246 0 9.020K 7.380K 8.130K 0.0000 4257496 3893946 9.0200 7.3800  
1388 RSRN28_3_4 8.200K 8.200K 2 R 179 251 0 9.020K 7.380K 8.090K 0.0000 6887070 5976299 9.0200 7.3800  
1389 RSRN28_5_6 8.200K 8.200K 2 R 634 249 0 9.020K 7.380K 8.070K 0.0000 2635612 2225763 9.0200 7.3800  
1390 RSRN28_7_8 8.200K 8.200K 2 R 634 248 0 9.020K 7.380K 8.070K 0.0000 2635612 2225763 9.0200 7.3800  

RUR730
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR730 A4 T 2 2 100.0  

Pin Nail Net Name
1 772 O_PWROK
2 379 P_USBPWR_SW

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1430 RUR730 10.00K 10.00K 2 R 772 379 0 11.00K 9.00K 10.10K 0.0000 2066968 1870161 11.000 9.0000  

RUR733
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR733 A4 T 2 2 100.0  

Pin Nail Net Name
1 706 +3VSB_ATX
2 378 USBPWR_SW_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1396 RUR733 8.200K 8.200K 2 R 706 378 0 9.020K 7.380K 8.240K 0.0057 47.727 45.350 9.0200 7.3800  

RUR755
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR755 A4 T 2 2 100.0  

Pin Nail Net Name
1 362 P_5VSB_USB_GATE_10_1
2 344 N16717240

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1182 RUR755 1.000K 1.000K 2 R 362 344 0 1.100K 0.900K 1.000K 0.0000 4240198 4114370 1.1000 0.9000  

RURN63
Device Loc Side Total Pin Tested Coverage (%) Comment
RURN63 B4 T 8 6 75.0 No Test Nail

Pin Nail Net Name
1 0 NC_2198
2 0 NC_2199
3 459 S_USB_OC_1112
4 309 +5V_USB_P1112_R
5 447 S_USB_OC_78
6 790 +5V_USB_P78_R
7 457 S_USB3_OC_34
8 739 +5V_USB_P34_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1255 RURN63/NP_1_ 4.700K 4.700K 2 R 0 0 0 5.170K 4.230K NA NA NA NA NA NA  
1256 RURN63_3_4 4.700K 4.700K 2 R 309 459 1 5.170K 4.230K 4.680K 0.0018 84.788 81.561 5.1700 4.2300  
1257 RURN63_5_6 4.700K 4.700K 2 R 790 447 1 5.170K 4.230K 4.680K 0.0000 2095553 1992025 5.1700 4.2300  
1258 RURN63_7_8 4.700K 4.700K 2 R 739 457 1 5.170K 4.230K 4.710K 0.0000 2032206 1993558 5.1700 4.2300  

RURN64
Device Loc Side Total Pin Tested Coverage (%) Comment
RURN64 B4 T 8 6 75.0 No Test Nail

Pin Nail Net Name
1 459 S_USB_OC_1112
2 1 GND
3 463 S_USB_OC_910
4 1 GND
5 0 NC_2181
6 0 NC_2182
7 447 S_USB_OC_78
8 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1397 RURN64/NP_5_ 8.200K 8.200K 2 R 0 0 0 9.020K 7.380K NA NA NA NA NA NA  
1398 RURN64_1_2 8.200K 8.200K 2 R 1 459 309 9.020K 7.380K 7.950K 0.0053 51.235 35.849 9.0200 7.3800  
1399 RURN64_3_4 8.200K 8.200K 2 R 1 463 203 9.020K 7.380K 7.970K 0.0054 50.997 36.834 9.0200 7.3800  
1400 RURN64_7_8 8.200K 8.200K 2 R 1 447 790 9.020K 7.380K 8.170K 0.0000 5220942 5022076 9.0200 7.3800  

RURN81
Device Loc Side Total Pin Tested Coverage (%) Comment
RURN81 B4 T 8 8 100.0  

Pin Nail Net Name
1 443 S_USB3_OC_12
2 965 +5V_USB3_P12
3 463 S_USB_OC_910
4 203 +5V_USB_P910
5 642 S_SMBDATA_SLOT
6 634 +3VSB
7 640 S_SMBCLK_SLOT
8 634 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1259 RURN81_1_2 4.700K 4.700K 2 R 965 443 1 5.170K 4.230K 4.660K 0.0018 85.485 78.560 5.1700 4.2300  
1260 RURN81_3_4 4.700K 4.700K 2 R 203 463 1 5.170K 4.230K 4.740K 0.0000 3322136 3028506 5.1700 4.2300  
1261 RURN81_5_6 4.700K 4.700K 2 R 634 642 0 5.170K 4.230K 4.680K 0.0000 2095553 1992025 5.1700 4.2300  
1262 RURN81_7_8 4.700K 4.700K 2 R 634 640 0 5.170K 4.230K 4.690K 0.0000 1836300 1783092 5.1700 4.2300  

RURN82
Device Loc Side Total Pin Tested Coverage (%) Comment
RURN82 B4 T 8 8 100.0  

Pin Nail Net Name
1 457 S_USB3_OC_34
2 1 GND
3 443 S_USB3_OC_12
4 1 GND
5 456 S_SATALED__R
6 2 +3V
7 440 N18996429
8 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1401 RURN82_1_2 8.200K 8.200K 2 R 1 457 739 9.020K 7.380K 8.100K 0.0000 2188027 1924212 9.0200 7.3800  
1402 RURN82_3_4 8.200K 8.200K 2 R 1 443 965 9.020K 7.380K 7.870K 0.0052 52.312 31.354 9.0200 7.3800  
1403 RURN82_5_6 8.200K 8.200K 2 R 2 456 0 9.020K 7.380K 8.090K 0.0000 6887070 5976299 9.0200 7.3800  
1404 RURN82_7_8 8.200K 8.200K 2 R 2 440 0 9.020K 7.380K 8.120K 0.0000 4711689 4253970 9.0200 7.3800