Transistor Tested Devices

QBQ14 QU31U5Q1 QU31U6Q1 QU31U6Q2 QU31U6Q7 QU31U6Q8 QU3CQ170 QU3CQ171 QU3CQ194 QU3EQ13
QAQ101 QGQ23 QGQX10 QGQX11 QGQX12 QGQX13 QK1PU1 QO1Q146 QO1Q171 QOQ202
QOQ203 QOQ300 QOQ310 QOQ311 QOQ320 QOQ321 QOQ760 QOQ761 QPQ111 QPQ114
QPQ121 QPQ122 QPQ131 QPQ134 QPQ211 QPQ213 QPQ221 QPQ223 QPQ304 QPQ306
QPQ403 QPQ404 QPQ410 QPQ506 QPQ511 QPQ512 QPQ514 QPQ515 QPQ516 QPQ520
QPQ521 QPQ522 QPQ523 QPQ532 QPQ533 QPQ601 QPQ602 QPQ603 QPQ604 QPQ605
QPQ606 QPQ607 QPQ608 QPQ609 QPQ610 QPQ611 QPQ612 QPQ613 QPQ614 QPQ615
QPQ620 QPQ621 QPQ622 QPQ624 QPQ625 QPQ704 QPQ705 QPQ706 QPQ707 QPQ708
QPQ709 QPQ710 QPQ711 QPQ712 QPQ801 QPQ803 QPQ805 QPQ806 QPQ807 QPQ808
QPQ809 QPQ810 QPQ811 QPU702 QQSWQ2 QQSWQ3 QSQ1 QSQ19 QSQ2 QSQ21
QSQ46 QSQ6 QSQ9 QUQ706 QUQ730 QUQ731        

QBQ14
Device Loc Side Total Pin Tested Coverage (%) Comment
QBQ14 A2 T 3 3 100.0  

Pin Nail Net Name
1 112 N41678282
2 1 GND
3 96 S_PME_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2858 QBQ14_1_2 0.700V 0.700V 0 Q 112 1 0 0.910V 0.490V 0.790V 0.0000 11537800 6805577 0.9100 0.4900  
2859 QBQ14_2_3 2.000V 0.300V 4 Q 96 1 112 0.390V Ignore 0.130V 0.0000 19606592 17666606 0.3900 0.2100  
2860 QBQ14_3_1 0.700V 0.700V 0 Q 112 96 0 0.910V 0.490V 0.780V 0.0000 10129079 6185884 0.9100 0.4900  

QU31U5Q1
Device Loc Side Total Pin Tested Coverage (%) Comment
QU31U5Q1 C1 T 3 3 100.0  

Pin Nail Net Name
1 767 U3C1_DFP_CC1_O
2 1 GND
3 752 U3C1_SEL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3355 QU31U5Q1_1_2 3000.0pF 1000.0pF 2 C 767 1 0 Ignore 700.0pF 782.4pF 39.343 2.5420 0.6990 1300.0 700.00  
3356 QU31U5Q1_2_3_ 5.000V 0.700V 4 Q 1 752 767 0.910V Ignore 0.290V 0.0002 415.26 402.08 0.9100 0.4900  
3357 QU31U5Q1_3_1( 0.700V 0.700V 1 Q 1 752 0 0.910V 0.490V 0.610V 0.0008 83.052 47.449 0.9100 0.4900  
3358 QU31U5Q1_3_1( 3000.0pF 30.00pF 2 C 767 752 0 Ignore 21.00pF 0.61pF 0.0008 83.052 47.449 0.9100 0.4900  

QU31U6Q1
Device Loc Side Total Pin Tested Coverage (%) Comment
QU31U6Q1 C1 T 3 3 100.0  

Pin Nail Net Name
1 746 N21438374
2 1 GND
3 762 U3C1_DFP_CC_PIN_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3359 QU31U6Q1_1_2 3000.0pF 100.00pF 2 C 746 1 0 Ignore 70.00pF 118.54pF 0.5844 17.112 6.5360 130.00 70.000  
3360 QU31U6Q1_2_3_ 5.000V 0.700V 4 Q 1 762 746 0.910V Ignore 0.290V 0.0002 415.26 403.81 0.9100 0.4900  
3361 QU31U6Q1_3_1( 0.700V 0.700V 0 Q 1 762 0 0.910V 0.490V 0.580V 0.0008 83.052 35.517 0.9100 0.4900  
3362 QU31U6Q1_3_1( 3000.0pF 30.00pF 2 C 746 762 0 Ignore 21.00pF 0.58pF 0.0008 83.052 35.517 0.9100 0.4900  

QU31U6Q2
Device Loc Side Total Pin Tested Coverage (%) Comment
QU31U6Q2 C2 T 3 3 100.0  

Pin Nail Net Name
1 792 N21438381
2 1 GND
3 762 U3C1_DFP_CC_PIN_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3363 QU31U6Q2_1_2 3000.0pF 80.00pF 2 C 792 1 0 Ignore 56.00pF 81.98pF 1.3265 6.0310 5.5340 104.00 56.000  
3364 QU31U6Q2_2_3_ 5.000V 0.700V 4 Q 1 762 792 0.910V Ignore 0.290V 0.0000 26863898 26135574 0.9100 0.4900  
3365 QU31U6Q2_3_1( 0.700V 0.700V 0 Q 1 762 0 0.910V 0.490V 0.550V 0.0008 83.052 22.815 0.9100 0.4900  
3366 QU31U6Q2_3_1( 3000.0pF 30.00pF 2 C 792 762 0 Ignore 21.00pF 0.55pF 0.0008 83.052 22.815 0.9100 0.4900  

QU31U6Q7
Device Loc Side Total Pin Tested Coverage (%) Comment
QU31U6Q7 C1 T 3 3 100.0  

Pin Nail Net Name
1 754 U3C1_O7
2 1 GND
3 753 N21574411

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3367 QU31U6Q7_1_2 3000.0pF 50.00pF 2 C 754 1 0 Ignore 35.00pF 56.20pF 3.8023 1.3150 0.7710 65.000 35.000  
3368 QU31U6Q7_2_3_ 5.000V 0.700V 4 Q 1 753 754 0.910V Ignore 0.290V 0.0002 415.26 399.77 0.9100 0.4900  
3369 QU31U6Q7_3_1( 0.700V 0.700V 0 Q 1 753 0 0.910V 0.490V 0.650V 0.0008 83.052 63.229 0.9100 0.4900  
3370 QU31U6Q7_3_1( 3000.0pF 50.00pF 2 C 754 753 0 Ignore 35.00pF 0.65pF 0.0008 83.052 63.229 0.9100 0.4900  

QU31U6Q8
Device Loc Side Total Pin Tested Coverage (%) Comment
QU31U6Q8 C2 T 3 3 100.0  

Pin Nail Net Name
1 771 U3C1_O8
2 1 GND
3 791 N21574180

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3371 QU31U6Q8_1_2 3000.0pF 50.00pF 2 C 771 1 0 Ignore 35.00pF 60.54pF 0.8677 5.7630 1.7120 65.000 35.000  
3372 QU31U6Q8_2_3_ 5.000V 0.700V 4 Q 1 791 771 0.910V Ignore 0.280V 0.0002 415.26 408.43 0.9100 0.4900  
3373 QU31U6Q8_3_1( 0.700V 0.700V 0 Q 1 791 0 0.910V 0.490V 0.640V 0.0022 31.391 22.153 0.9100 0.4900  
3374 QU31U6Q8_3_1( 3000.0pF 30.00pF 2 C 771 791 0 Ignore 21.00pF 0.64pF 0.0022 31.391 22.153 0.9100 0.4900  

QU3CQ170
Device Loc Side Total Pin Tested Coverage (%) Comment
QU3CQ170 C1 T 3 3 100.0  

Pin Nail Net Name
1 752 U3C1_SEL
2 1 GND
3 798 GP_TYPEC_CC_DETECT_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3375 QU3CQ170_1_2 3000.0pF 2000.0pF 2 C 752 1 0 Ignore 1400.0pF 1794.2pF 22.080 9.0580 5.9510 2600.0 1400.0  
3376 QU3CQ170_2_3_ 5.000V 0.700V 4 Q 1 798 752 0.910V Ignore 0.460V 0.0003 239.75 37.583 0.9100 0.4900  
3377 QU3CQ170_3_1( 0.700V 0.700V 0 Q 1 798 0 0.910V 0.490V 0.590V 0.0000 9853331 4647539 0.9100 0.4900  
3378 QU3CQ170_3_1( 3000.0pF 30.00pF 2 C 752 798 0 Ignore 21.00pF 0.59pF 0.0000 9853331 4647539 0.9100 0.4900  

QU3CQ171
Device Loc Side Total Pin Tested Coverage (%) Comment
QU3CQ171 C2 T 3 3 100.0  

Pin Nail Net Name
1 793 U3C1_DFP_CC2_O
2 1 GND
3 799 GP_TYPEC_CC_DETECT_2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3379 QU3CQ171_1_2 3000.0pF 80.00pF 2 C 793 1 0 Ignore 56.00pF 85.57pF 3.3051 2.4200 1.8590 104.00 56.000  
3380 QU3CQ171_2_3_ 5.000V 0.700V 4 Q 1 799 793 0.910V Ignore 0.300V 0.0002 415.26 373.79 0.9100 0.4900  
3381 QU3CQ171_3_1( 0.700V 0.700V 0 Q 1 799 0 0.910V 0.490V 0.630V 0.0008 83.052 56.686 0.9100 0.4900  
3382 QU3CQ171_3_1( 3000.0pF 30.00pF 2 C 793 799 0 Ignore 21.00pF 0.63pF 0.0008 83.052 56.686 0.9100 0.4900  

QU3CQ194
Device Loc Side Total Pin Tested Coverage (%) Comment
QU3CQ194 C1 T 3 3 100.0  

Pin Nail Net Name
1 762 U3C1_DFP_CC_PIN_
2 1 GND
3 795 U3C1_PSW_EN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3383 QU3CQ194_1_2 3000.0pF 100.00pF 2 C 762 1 0 Ignore 70.00pF 116.86pF 1.4509 6.8920 3.0190 130.00 70.000  
3384 QU3CQ194_2_3_ 5.000V 0.700V 4 Q 1 795 762 0.910V Ignore 0.030V 0.0002 415.26 909.95 0.9100 0.4900  
3385 QU3CQ194_3_1( 0.700V 0.700V 0 Q 1 795 0 0.910V 0.490V 0.590V 0.0000 25409368 12338162 0.9100 0.4900  
3386 QU3CQ194_3_1( 3000.0pF 100.00pF 2 C 762 795 0 Ignore 70.00pF 0.59pF 0.0000 25409368 12338162 0.9100 0.4900  

QU3EQ13
Device Loc Side Total Pin Tested Coverage (%) Comment
QU3EQ13 C1 T 3 3 100.0  

Pin Nail Net Name
1 849 GP_TYPEC_PWR_CTL
2 1 GND
3 762 U3C1_DFP_CC_PIN_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3387 QU3EQ13_1_2 3000.0pF 3000.0pF 2 C 849 1 0 Ignore 2100.0pF 5073.9pF 20.566 14.587 19.026 3900.0 2100.0  
3388 QU3EQ13_2_3_1 5.000V 0.700V 4 Q 1 762 849 0.910V Ignore 0.510V 0.0002 415.26 32.668 0.9100 0.4900  
3389 QU3EQ13_3_1(N 0.700V 0.700V 0 Q 1 762 0 0.910V 0.490V 0.560V 0.0008 83.052 27.819 0.9100 0.4900  
3390 QU3EQ13_3_1(N 3000.0pF 330.00pF 1 C 849 762 0 Ignore 231.00pF 0.56pF 0.0008 83.052 27.819 0.9100 0.4900  

QAQ101
Device Loc Side Total Pin Tested Coverage (%) Comment
QAQ101 A1 T 3 3 100.0  

Pin Nail Net Name
1 47 AUDIO_LED_PWM
2 1 GND
3 708 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2854 QAQ101_1_2 3000.0pF 1000.0pF 2 C 47 1 0 Ignore 700.0pF 853.7pF 46.058 2.1710 1.1130 1300.0 700.00  
2855 QAQ101_2_3_1 5.000V 0.300V 4 Q 1 708 47 0.390V Ignore 0.030V 0.0000 121904040 244302416 0.3900 0.2100  
2856 QAQ101_3_1(N) 0.700V 0.700V 0 Q 1 708 0 0.910V 0.490V 0.610V 0.0008 83.052 46.871 0.9100 0.4900  
2857 QAQ101_3_1(N) 3000.0pF 30.00pF 2 C 47 708 0 Ignore 21.00pF 0.61pF 0.0008 83.052 46.871 0.9100 0.4900  

QGQ23
Device Loc Side Total Pin Tested Coverage (%) Comment
QGQ23 E1 T 3 3 100.0  

Pin Nail Net Name
1 4 +12V
2 3 +5V
3 1279 +5V_DVI_HDMI_Q

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2861 QGQ23_1_2 3000.0pF 1000.0pF 2 C 4 3 0 Ignore 700.0pF 866.0pF 43.435 2.3020 1.2740 1300.0 700.00  
2862 QGQ23_2_3_1(N 5.000V 0.400V 4 Q 3 1279 4 0.520V Ignore 0.360V 0.0023 17.541 12.313 0.5200 0.2800  
2863 QGQ23_3_1 0.700V 0.700V 0 Q 4 1279 0 0.910V 0.490V 0.660V 0.0030 23.034 18.177 0.9100 0.4900  
2864 QGQ23_3_1 3000.0pF 1600.0pF 2 C 4 1279 0 Ignore 1120.0pF 0.7pF 0.0030 23.034 18.177 0.9100 0.4900  

QGQX10
Device Loc Side Total Pin Tested Coverage (%) Comment
QGQX10 E1 T 3 3 100.0  

Pin Nail Net Name
1 2 +3V
2 1253 S_DVI_DDC_DATA
3 1285 SW_DVI_DDC_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2865 QGQX10_1_2 3000.0pF 600.00pF 2 C 2 1253 0 Ignore 420.00pF 649.93pF 0.2735 219.35 158.51 780.00 420.00  
2866 QGQX10_2_3_1 5.000V 0.500V 4 Q 1253 1285 2 0.650V Ignore 0.490V 0.0003 171.25 156.58 0.6500 0.3500  
2867 QGQX10_3_1(N) 0.700V 0.700V 0 Q 1253 1285 0 0.910V 0.490V 0.640V 0.0008 83.052 58.033 0.9100 0.4900  
2868 QGQX10_3_1(N) 3000.0pF 600.00pF 2 C 2 1285 0 Ignore 420.00pF 0.64pF 0.0008 83.052 58.033 0.9100 0.4900  

QGQX11
Device Loc Side Total Pin Tested Coverage (%) Comment
QGQX11 E1 T 3 3 100.0  

Pin Nail Net Name
1 2 +3V
2 1278 S_DVI_DDC_CLK
3 1286 SW_DVI_DDC_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2869 QGQX11_1_2 3000.0pF 600.00pF 2 C 2 1278 0 Ignore 420.00pF 630.82pF 0.0000 112544984 93275144 780.00 420.00  
2870 QGQX11_2_3_1 5.000V 0.700V 4 Q 1278 1286 2 0.910V Ignore 0.460V 0.0003 239.75 33.583 0.9100 0.4900  
2871 QGQX11_3_1(N) 0.700V 0.700V 0 Q 1278 1286 0 0.910V 0.490V 0.630V 0.0008 83.052 54.569 0.9100 0.4900  
2872 QGQX11_3_1(N) 3000.0pF 600.00pF 2 C 2 1286 0 Ignore 420.00pF 0.63pF 0.0008 83.052 54.569 0.9100 0.4900  

QGQX12
Device Loc Side Total Pin Tested Coverage (%) Comment
QGQX12 E1 T 3 3 100.0  

Pin Nail Net Name
1 2 +3V
2 742 S_DVI_HPD
3 1283 SW_DVI_HPD

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2873 QGQX12_1_2 3000.0pF 200.00pF 2 C 2 742 0 Ignore 140.00pF 210.02pF 0.4130 48.424 40.337 260.00 140.00  
2874 QGQX12_2_3_1 5.000V 0.700V 4 Q 742 1283 2 0.910V Ignore 0.440V 0.0003 239.75 60.917 0.9100 0.4900  
2875 QGQX12_3_1(N) 0.700V 0.700V 0 Q 742 1283 0 0.910V 0.490V 0.600V 0.0015 47.950 24.617 0.9100 0.4900  
2876 QGQX12_3_1(N) 3000.0pF 150.00pF 2 C 2 1283 0 Ignore 105.00pF 0.60pF 0.0015 47.950 24.617 0.9100 0.4900  

QGQX13
Device Loc Side Total Pin Tested Coverage (%) Comment
QGQX13 E1 T 3 3 100.0  

Pin Nail Net Name
1 2 +3V
2 1 GND
3 1297 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2877 QGQX13_1_2 3000.0pF 700.00pF 1 C 1297 1 0 Ignore 490.00pF 662.44pF 19.999 3.5000 2.8740 910.00 490.00  
2878 QGQX13_2_3_1 5.000V 0.700V 4 Q 1 1297 2 0.910V Ignore 0.620V 0.0003 239.75 152.42 0.9100 0.4900  
2879 QGQX13_3_1(N) 0.700V 0.700V 0 Q 2 1297 0 0.910V 0.490V 0.660V 0.0000 21641096 17278276 0.9100 0.4900  
2880 QGQX13_3_1(N) 3000.0pF 600.00pF 2 C 2 1297 0 Ignore 420.00pF 0.66pF 0.0000 21641096 17278276 0.9100 0.4900  

QK1PU1
Device Loc Side Total Pin Tested Coverage (%) Comment
QK1PU1 B2 T 5 5 100.0 C

Pin Nail Net Name
1 607 1083_CORE_PWR_EN
2 1 GND
3 2 +3V
4 605 +1_2V_EPCI
5 606 K1_1V2_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2884 QK1PU1_1_2 0.700V 0.700V 0 Q 1 607 0 0.910V 0.490V 0.700V 0.0000 7686209 7632777 0.9100 0.4900  
2885 QK1PU1_2_3/C 0.700V 0.700V 0 Q 1 2 0 0.910V 0.490V NA NA NA NA NA NA  
2886 QK1PU1_3_4 0.700V 0.700V 1 Q 605 2 0 0.910V 0.490V 0.710V 0.0000 9906679 9631206 0.9100 0.4900  
2887 QK1PU1_4_5 0.700V 0.700V 0 Q 605 606 0 0.910V 0.490V 0.810V 0.0000 5373852 2572052 0.9100 0.4900  

QO1Q146
Device Loc Side Total Pin Tested Coverage (%) Comment
QO1Q146 B1 T 3 3 100.0  

Pin Nail Net Name
1 676 O_MEMOK_
2 1 GND
3 378 USBPWR_SW_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2888 QO1Q146_1_2 3000.0pF 50.00pF 2 C 676 1 0 Ignore 35.00pF 55.91pF 0.8637 5.7890 3.5070 65.000 35.000  
2889 QO1Q146_2_3_1 5.000V 0.300V 4 Q 1 378 676 0.390V Ignore 0.030V 0.0003 102.75 200.92 0.3900 0.2100  
2890 QO1Q146_3_1(N 0.700V 0.700V 0 Q 1 378 0 0.910V 0.490V 0.640V 0.0008 83.052 59.765 0.9100 0.4900  
2891 QO1Q146_3_1(N 3000.0pF 30.00pF 2 C 676 378 0 Ignore 21.00pF 0.64pF 0.0008 83.052 59.765 0.9100 0.4900  

QO1Q171
Device Loc Side Total Pin Tested Coverage (%) Comment
QO1Q171 A1 T 3 3 100.0  

Pin Nail Net Name
1 3 +5V
2 79 O_COM1_RI1__Q
3 657 LAN_SIO_WAKE_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2895 QO1Q171_1_2 3000.0pF 1000.0pF 2 C 3 79 0 Ignore 700.0pF 915.4pF 0.9012 110.96 79.664 1300.0 700.00  
2896 QO1Q171_2_3_1 5.000V 0.700V 4 Q 79 657 3 0.910V Ignore 0.590V 0.0003 207.63 101.49 0.9100 0.4900  
2897 QO1Q171_3_1(N 0.700V 0.700V 0 Q 79 657 0 0.910V 0.490V 0.640V 0.0008 83.052 58.611 0.9100 0.4900  
2898 QO1Q171_3_1(N 3000.0pF 300.00pF 2 C 3 657 0 Ignore 210.00pF 0.64pF 0.0008 83.052 58.611 0.9100 0.4900  

QOQ202
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ202 A4 T 3 3 100.0  

Pin Nail Net Name
1 370 S_SPKR_R
2 1 GND
3 363 SPKO-_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2908 QOQ202_1_2 0.700V 0.700V 0 Q 370 1 0 0.910V 0.490V 0.790V 0.0000 12202914 7028233 0.9100 0.4900  
2909 QOQ202_2_3 1.500V 0.300V 4 Q 363 1 370 0.390V Ignore 0.120V 0.0000 28699628 28187552 0.3900 0.2100  
2910 QOQ202_3_1 0.700V 0.700V 0 Q 370 363 0 0.910V 0.490V 0.780V 0.0008 83.052 50.335 0.9100 0.4900  

QOQ203
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ203 A4 T 3 3 100.0  

Pin Nail Net Name
1 371 O_PLED_R
2 1 GND
3 226 PLED-

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2911 QOQ203_1_2 0.700V 0.700V 0 Q 371 1 0 0.910V 0.490V 0.790V 0.0000 7047291 4107857 0.9100 0.4900  
2912 QOQ203_2_3 1.500V 0.300V 4 Q 226 1 371 0.390V Ignore 0.130V 0.0002 177.97 154.78 0.3900 0.2100  
2913 QOQ203_3_1 0.782V 0.700V 0 Q 371 226 0 0.910V 0.490V 0.780V 0.0008 83.052 50.335 0.9100 0.4900  

QOQ300
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ300 F1 T 3 3 100.0  

Pin Nail Net Name
1 1695 O_CPUFAN_PWM_B
2 787 O_CPUFAN_PWM
3 1653 O_CPUFAN_PWM_Q

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2917 QOQ300_1_2 0.700V 0.700V 0 Q 1695 787 0 0.910V 0.490V 0.790V 0.0008 83.052 48.218 0.9100 0.4900  
2918 QOQ300_2_3 2.000V 0.300V 4 Q 1653 787 1695 0.390V Ignore 0.140V 0.0000 26686198 21708240 0.3900 0.2100  
2919 QOQ300_3_1 0.700V 0.700V 0 Q 1695 1653 0 0.910V 0.490V 0.780V 0.0000 5883753 3634142 0.9100 0.4900  

QOQ310
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ310 F4 T 3 3 100.0  

Pin Nail Net Name
1 1516 O_CHAFAN_PWM_B
2 1694 O_CHAFAN_PWM
3 1581 O_CHAFAN_PWM_Q

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2920 QOQ310_1_2 0.700V 0.700V 0 Q 1516 1694 0 0.910V 0.490V 0.790V 0.0000 12202914 7028233 0.9100 0.4900  
2921 QOQ310_2_3 1.500V 0.300V 4 Q 1581 1694 1516 0.390V Ignore 0.150V 0.0002 177.97 116.10 0.3900 0.2100  
2922 QOQ310_3_1 0.700V 0.700V 0 Q 1516 1581 0 0.910V 0.490V 0.780V 0.0008 83.052 50.913 0.9100 0.4900  

QOQ311
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ311 F4 T 3 3 100.0  

Pin Nail Net Name
1 1514 GP_CHAFAN_PWM_DC_
2 1 GND
3 1547 O_CHAFAN_EN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2923 QOQ311_1_2 3000.0pF 2000.0pF 2 C 1514 1 0 Ignore 1400.0pF 1912.1pF 36.058 5.5470 4.7340 2600.0 1400.0  
2924 QOQ311_2_3_1 5.000V 0.700V 4 Q 1 1547 1514 0.910V Ignore 0.480V 0.0002 415.26 20.833 0.9100 0.4900  
2925 QOQ311_3_1(N) 0.700V 0.700V 0 Q 1 1547 0 0.910V 0.490V 0.610V 0.0000 6401108 3642201 0.9100 0.4900  
2926 QOQ311_3_1(N) 3000.0pF 30.00pF 2 C 1514 1547 0 Ignore 21.00pF 0.61pF 0.0000 6401108 3642201 0.9100 0.4900  

QOQ320
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ320 B1 T 3 3 100.0  

Pin Nail Net Name
1 654 O_CHAFAN_PWM2_B
2 691 O_CHAFAN_PWM2
3 743 O_CHAFAN_PWM2_Q

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2927 QOQ320_1_2 0.700V 0.700V 0 Q 654 691 0 0.910V 0.490V 0.790V 0.0000 7047291 4107857 0.9100 0.4900  
2928 QOQ320_2_3 1.500V 0.300V 4 Q 743 691 654 0.390V Ignore 0.140V 0.0000 19933814 15956753 0.3900 0.2100  
2929 QOQ320_3_1 0.700V 0.700V 0 Q 654 743 0 0.910V 0.490V 0.780V 0.0000 10129079 6185884 0.9100 0.4900  

QOQ321
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ321 B1 T 3 3 100.0  

Pin Nail Net Name
1 651 GP_CHAFAN_PWM_DC_2
2 1 GND
3 653 O_CHAFAN_EN2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2930 QOQ321_1_2 3000.0pF 2000.0pF 2 C 651 1 0 Ignore 1400.0pF 1909.7pF 41.450 4.8250 4.0990 2600.0 1400.0  
2931 QOQ321_2_3_1 5.000V 0.700V 4 Q 1 653 651 0.910V Ignore 0.470V 0.0003 207.63 17.152 0.9100 0.4900  
2932 QOQ321_3_1(N) 0.700V 0.700V 1 Q 1 653 0 0.910V 0.490V 0.720V 0.0008 83.052 76.509 0.9100 0.4900  
2933 QOQ321_3_1(N) 3000.0pF 50.00pF 2 C 651 653 0 Ignore 35.00pF 0.72pF 0.0008 83.052 76.509 0.9100 0.4900  

QOQ760
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ760 A2 T 3 3 100.0  

Pin Nail Net Name
1 118 O_DEEP_S5_C
2 634 +3VSB
3 706 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2934 QOQ760_1_2 3000.0pF 1000.0pF 2 C 118 634 0 Ignore 700.0pF 977.8pF 1.6247 61.549 57.000 1300.0 700.00  
2935 QOQ760_2_3_1 5.000V 0.700V 3 Q 634 706 118 0.910V Ignore 0.640V 0.0008 90.617 62.900 0.9100 0.4900  
2936 QOQ760_3_1(P) 0.700V 0.700V 1 Q 634 706 0 0.910V 0.490V 0.610V 0.0000 8250093 4522210 0.9100 0.4900  
2937 QOQ760_3_1(P) 3000.0pF 1000.0pF 2 C 118 706 0 Ignore 700.0pF 0.6pF 0.0000 8250093 4522210 0.9100 0.4900  

QOQ761
Device Loc Side Total Pin Tested Coverage (%) Comment
QOQ761 A1 T 3 3 100.0  

Pin Nail Net Name
1 1 GND
2 5 -12V
3 97 O_DEEP_S5_12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2938 QOQ761_1_2 3000.0pF 1000.0pF 2 C 1 5 0 Ignore 700.0pF 1251.3pF 6.3567 15.731 2.5560 1300.0 700.00  
2939 QOQ761_2_3_1 5.000V 0.700V 4 Q 5 1 97 0.910V Ignore 0.700V 0.0017 41.526 40.583 0.9100 0.4900  
2940 QOQ761_3_1(N) 0.700V 0.700V 0 Q 5 97 0 0.910V 0.490V 0.660V 0.0000 16728486 13472334 0.9100 0.4900  
2941 QOQ761_3_1(N) 3000.0pF 1000.0pF 2 C 5 97 0 Ignore 700.0pF 0.7pF 0.0000 16728486 13472334 0.9100 0.4900  

QPQ111
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ111 E1 T 5 5 100.0  

Pin Nail Net Name
1 1320 P_VCORE_PHASE1_20
2 1320 P_VCORE_PHASE1_20
3 1320 P_VCORE_PHASE1_20
4 1693 P_VCORE_R_HG1_20
5 1316 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2942 QPQ111_3_4 3000.0pF 1000.0pF 2 C 1320 1693 0 Ignore 700.0pF 1387.3pF 0.7805 128.12 37.295 1300.0 700.00  
2943 QPQ111_4_5_1 5.000V 0.300V 4 Q 1320 1316 1693 0.390V Ignore -0.010V 0.0028 10.771 26.303 0.3900 0.2100  
2944 QPQ111_5_1(N) 0.700V 0.700V 0 Q 1316 1693 0 0.910V 0.490V 0.710V 0.0000 7563614 7248134 0.9100 0.4900  
2945 QPQ111_5_1(N) 3000.0pF 3000.0pF 2 C 1693 1316 0 Ignore 2100.0pF 0.7pF 0.0000 7563614 7248134 0.9100 0.4900  

QPQ114
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ114 E2 T 5 5 100.0  

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1321 P_VCORE_LG1_20
5 1320 P_VCORE_PHASE1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2951 QPQ114_3_4 3000.0pF 3000.0pF 2 C 1321 1 0 Ignore 2100.0pF 4875.4pF 25.085 11.959 12.960 3900.0 2100.0  
2952 QPQ114_4_5_1 5.000V 0.300V 4 Q 1 1320 1321 0.390V Ignore -0.030V 0.0053 5.7000 15.342 0.3900 0.2100  
2953 QPQ114_5_1(N) 0.700V 0.700V 0 Q 1320 1321 0 0.910V 0.490V 0.690V 0.0053 13.299 12.652 0.9100 0.4900  
2954 QPQ114_5_1(N) 3000.0pF 3000.0pF 2 C 1321 1320 0 Ignore 2100.0pF 0.7pF 0.0053 13.299 12.652 0.9100 0.4900  

QPQ121
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ121 E1 T 5 5 100.0  

Pin Nail Net Name
1 1319 P_VCORE_PHASE2_20
2 1319 P_VCORE_PHASE2_20
3 1319 P_VCORE_PHASE2_20
4 1313 P_VCORE_R_HG2_20
5 1316 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2955 QPQ121_3_4 3000.0pF 3000.0pF 2 C 1313 1319 0 Ignore 2100.0pF 3645.8pF 29.580 10.142 2.8640 3900.0 2100.0  
2956 QPQ121_4_5_1 5.000V 0.300V 4 Q 1319 1316 1313 0.390V Ignore 0.000V 0.0011 27.140 62.901 0.3900 0.2100  
2957 QPQ121_5_1(N) 0.700V 0.600V 0 Q 1316 1313 0 0.780V 0.420V 0.460V 0.0008 71.187 15.281 0.7800 0.4200  
2958 QPQ121_5_1(N) 3000.0pF 3000.0pF 2 C 1313 1316 0 Ignore 2100.0pF 0.5pF 0.0008 71.187 15.281 0.7800 0.4200  

QPQ122
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ122 E2 T 5 5 100.0  

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1314 P_VCORE_LG2_20
5 1319 P_VCORE_PHASE2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2959 QPQ122_3_4 3000.0pF 3000.0pF 2 C 1314 1 0 Ignore 2100.0pF 4922.4pF 20.507 14.629 16.619 3900.0 2100.0  
2960 QPQ122_4_5_1 5.000V 0.300V 4 Q 1 1319 1314 0.390V Ignore -0.020V 0.0050 6.0230 15.432 0.3900 0.2100  
2961 QPQ122_5_1(N) 0.700V 0.700V 0 Q 1319 1314 0 0.910V 0.490V 0.630V 0.0022 31.391 20.771 0.9100 0.4900  
2962 QPQ122_5_1(N) 3000.0pF 3000.0pF 2 C 1314 1319 0 Ignore 2100.0pF 0.6pF 0.0022 31.391 20.771 0.9100 0.4900  

QPQ131
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ131 E1 T 5 5 100.0  

Pin Nail Net Name
1 1199 P_VCORE_PHASE3_20
2 1199 P_VCORE_PHASE3_20
3 1199 P_VCORE_PHASE3_20
4 1317 P_VCORE_R_HG3_20
5 1316 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2968 QPQ131_3_4 3000.0pF 3000.0pF 2 C 1317 1199 0 Ignore 2100.0pF 3778.0pF 88.856 3.3760 0.4580 3900.0 2100.0  
2969 QPQ131_4_5_1 5.000V 0.300V 4 Q 1199 1316 1317 0.390V Ignore -0.030V 0.0006 49.360 130.09 0.3900 0.2100  
2970 QPQ131_5_1(N) 0.700V 0.700V 0 Q 1316 1317 0 0.910V 0.490V 0.630V 0.0080 8.7060 5.8410 0.9100 0.4900  
2971 QPQ131_5_1(N) 3000.0pF 3000.0pF 2 C 1317 1316 0 Ignore 2100.0pF 0.6pF 0.0080 8.7060 5.8410 0.9100 0.4900  

QPQ134
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ134 D2 T 5 5 100.0  

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1227 P_VCORE_LG3_20
5 1199 P_VCORE_PHASE3_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2977 QPQ134_3_4 3000.0pF 3000.0pF 2 C 1227 1 0 Ignore 2100.0pF 4982.8pF 23.934 12.535 15.081 3900.0 2100.0  
2978 QPQ134_4_5_1 5.000V 0.300V 4 Q 1 1199 1227 0.390V Ignore 0.000V 0.0048 6.2260 14.646 0.3900 0.2100  
2979 QPQ134_5_1(N) 0.700V 0.700V 0 Q 1199 1227 0 0.910V 0.490V 0.630V 0.0039 18.123 12.328 0.9100 0.4900  
2980 QPQ134_5_1(N) 3000.0pF 3000.0pF 2 C 1227 1199 0 Ignore 2100.0pF 0.6pF 0.0039 18.123 12.328 0.9100 0.4900  

QPQ211
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ211 F2 T 5 5 100.0  

Pin Nail Net Name
1 1657 P_GT_PHASE1_20
2 1657 P_GT_PHASE1_20
3 1657 P_GT_PHASE1_20
4 1655 P_GT_R_HG1_R_20
5 1316 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2981 QPQ211_3_4 3000.0pF 3000.0pF 2 C 1655 1657 0 Ignore 2100.0pF 3686.7pF 34.519 8.6910 2.0600 3900.0 2100.0  
2982 QPQ211_4_5_1 5.000V 0.300V 4 Q 1657 1316 1655 0.390V Ignore -0.070V 0.0033 9.1420 28.473 0.3900 0.2100  
2983 QPQ211_5_1(N) 0.700V 0.700V 0 Q 1316 1655 0 0.910V 0.490V 0.560V 0.0152 4.6140 1.5350 0.9100 0.4900  
2984 QPQ211_5_1(N) 3000.0pF 3000.0pF 2 C 1655 1316 0 Ignore 2100.0pF 0.6pF 0.0152 4.6140 1.5350 0.9100 0.4900  

QPQ213
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ213 F2 T 5 5 100.0  

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1662 P_GT_LG1_20
5 1657 P_GT_PHASE1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2990 QPQ213_3_4 3000.0pF 3000.0pF 2 C 1662 1 0 Ignore 2100.0pF 3397.4pF 11.948 25.109 14.023 3900.0 2100.0  
2991 QPQ213_4_5_1 5.000V 0.300V 4 Q 1 1657 1662 0.390V Ignore -0.010V 0.0060 5.0000 12.383 0.3900 0.2100  
2992 QPQ213_5_1(N) 0.700V 0.700V 0 Q 1657 1662 0 0.910V 0.490V 0.620V 0.0076 9.2280 5.7000 0.9100 0.4900  
2993 QPQ213_5_1(N) 3000.0pF 3000.0pF 2 C 1662 1657 0 Ignore 2100.0pF 0.6pF 0.0076 9.2280 5.7000 0.9100 0.4900  

QPQ221
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ221 F2 T 5 5 100.0  

Pin Nail Net Name
1 1671 P_GT_PHASE2_20
2 1671 P_GT_PHASE2_20
3 1671 P_GT_PHASE2_20
4 1668 P_GT_R_HG2_R_20
5 1316 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2994 QPQ221_3_4 3000.0pF 3000.0pF 2 C 1668 1671 0 Ignore 2100.0pF 3515.2pF 84.641 3.5440 1.5150 3900.0 2100.0  
2995 QPQ221_4_5_1 5.000V 0.300V 4 Q 1671 1316 1668 0.390V Ignore -0.060V 0.0110 2.7150 8.0680 0.3900 0.2100  
2996 QPQ221_5_1(N) 0.700V 0.700V 0 Q 1316 1668 0 0.910V 0.490V 0.580V 0.0704 0.9950 0.4180 0.9100 0.4900  
2997 QPQ221_5_1(N) 3000.0pF 3000.0pF 2 C 1668 1316 0 Ignore 2100.0pF 0.6pF 0.0704 0.9950 0.4180 0.9100 0.4900  

QPQ223
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ223 F2 T 5 5 100.0  

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1670 P_GT_LG2_20
5 1671 P_GT_PHASE2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3003 QPQ223_3_4 3000.0pF 3000.0pF 2 C 1670 1 0 Ignore 2100.0pF 3461.4pF 69.303 4.3290 2.1100 3900.0 2100.0  
3004 QPQ223_4_5_1 5.000V 0.300V 4 Q 1 1671 1670 0.390V Ignore 0.000V 0.0033 9.0470 21.329 0.3900 0.2100  
3005 QPQ223_5_1(N) 0.700V 0.700V 0 Q 1671 1670 0 0.910V 0.490V 0.630V 0.0008 83.052 57.264 0.9100 0.4900  
3006 QPQ223_5_1(N) 3000.0pF 3000.0pF 2 C 1670 1671 0 Ignore 2100.0pF 0.6pF 0.0008 83.052 57.264 0.9100 0.4900  

QPQ304
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ304 B4 T 3 3 100.0  

Pin Nail Net Name
1 432 P_VCCIO_PG_G2_10
2 1 GND
3 1519 P_+VCCIO_PG_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3020 QPQ304_1_2 3000.0pF 100.00pF 2 C 432 1 0 Ignore 70.00pF 114.39pF 3.5143 2.8460 1.4800 130.00 70.000  
3021 QPQ304_2_3_1 5.000V 0.700V 4 Q 1 1519 432 0.910V Ignore 0.030V 0.0002 415.26 903.60 0.9100 0.4900  
3022 QPQ304_3_1(N) 0.700V 0.700V 1 Q 1 1519 0 0.910V 0.490V 0.680V 0.0008 83.052 74.584 0.9100 0.4900  
3023 QPQ304_3_1(N) 3000.0pF 120.00pF 2 C 432 1519 0 Ignore 84.00pF 0.68pF 0.0008 83.052 74.584 0.9100 0.4900  

QPQ306
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ306 C4 T 3 3 100.0  

Pin Nail Net Name
1 923 P_VCCIO_PG_G1_10
2 1 GND
3 432 P_VCCIO_PG_G2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3027 QPQ306_1_2 0.700V 0.700V 0 Q 923 1 0 0.910V 0.490V 0.790V 0.0000 11537800 6805577 0.9100 0.4900  
3028 QPQ306_2_3 1.500V 0.300V 4 Q 432 1 923 0.390V Ignore 0.180V 0.0015 20.023 7.1720 0.3900 0.2100  
3029 QPQ306_3_1 0.700V 0.700V 0 Q 923 432 0 0.910V 0.490V 0.780V 0.0000 5883753 3634142 0.9100 0.4900  

QPQ403
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ403 B2 T 3 3 100.0  

Pin Nail Net Name
1 611 P_3V_GATE_10
2 2 +3V
3 164 +3V_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3033 QPQ403_1_2 3000.0pF 2000.0pF 2 C 611 2 0 Ignore 1400.0pF 1819.7pF 2.7037 73.973 51.746 2600.0 1400.0  
3034 QPQ403_2_3_1 5.000V 0.500V 3 Q 164 2 611 0.650V Ignore 0.460V 0.0002 296.61 225.99 0.6500 0.3500  
3035 QPQ403_3_1(P) 0.700V 0.700V 1 Q 2 164 0 0.910V 0.490V 0.640V 0.0000 13838432 10182817 0.9100 0.4900  
3036 QPQ403_3_1(P) 3000.0pF 3000.0pF 2 C 611 164 0 Ignore 2100.0pF 0.6pF 0.0000 13838432 10182817 0.9100 0.4900  

QPQ404
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ404 B2 T 3 3 100.0  

Pin Nail Net Name
1 610 P_+3V_OV_G1_10
2 164 +3V_ATX
3 611 P_3V_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3037 QPQ404_1_2 0.700V 0.700V 0 Q 164 610 0 0.910V 0.490V 0.790V 0.0000 19824122 11279835 0.9100 0.4900  
3038 QPQ404_2_3 1.500V 0.300V 3 Q 611 164 610 0.390V Ignore 0.140V 0.0000 51411240 37651544 0.3900 0.2100  
3039 QPQ404_3_1 0.700V 0.700V 0 Q 611 610 0 0.910V 0.490V 0.780V 0.0000 6787477 4050781 0.9100 0.4900  

QPQ410
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ410 B2 T 3 3 100.0  

Pin Nail Net Name
1 608 P_+3V_OV_REF_10
2 626 P_+3V_OV_E_10
3 609 P_+3V_OV_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3040 QPQ410_1_2 0.700V 0.700V 0 Q 608 626 0 0.910V 0.490V 0.780V 0.0000 6614434 3993490 0.9100 0.4900  
3041 QPQ410_2_3 5.000V 0.300V 4 Q 609 626 608 0.390V Ignore 0.070V 0.0002 177.97 284.10 0.3900 0.2100  
3042 QPQ410_3_1 0.700V 0.700V 0 Q 608 609 0 0.910V 0.490V 0.780V 0.0000 15525381 9805219 0.9100 0.4900  

QPQ506
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ506 F4 T 3 3 100.0  

Pin Nail Net Name
1 1504 P_SLP_S4__R1_10
2 1 GND
3 1505 P_+VDDQ_C1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3046 QPQ506_1_2 0.700V 0.700V 0 Q 1504 1 0 0.910V 0.490V 0.790V 0.0000 7047291 4107857 0.9100 0.4900  
3047 QPQ506_2_3 1.500V 0.300V 4 Q 1505 1 1504 0.390V Ignore 0.120V 0.0000 51799256 53563712 0.3900 0.2100  
3048 QPQ506_3_1 0.700V 0.700V 0 Q 1504 1505 0 0.910V 0.490V 0.780V 0.0000 5883753 3634142 0.9100 0.4900  

QPQ511
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ511 F4 T 5 5 100.0  

Pin Nail Net Name
1 1490 P_VDDQ_PHASE_20
2 1490 P_VDDQ_PHASE_20
3 1490 P_VDDQ_PHASE_20
4 1493 P_VDDQ_UGATE_M_20
5 1495 P_VDDQ_REGIN_S

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3049 QPQ511_3_4 3000.0pF 1300.0pF 2 C 1490 1493 0 Ignore 910.0pF 1344.4pF 0.0000 13240072 11732774 1690.0 910.00  
3050 QPQ511_4_5_1 5.000V 0.300V 4 Q 1490 1495 1493 0.390V Ignore 0.020V 0.0004 67.266 141.64 0.3900 0.2100  
3051 QPQ511_5_1(N) 0.700V 0.700V 0 Q 1495 1493 0 0.910V 0.490V 0.490V 0.0000 19168598 379774 0.9100 0.4900  
3052 QPQ511_5_1(N) 3000.0pF 3000.0pF 2 C 1493 1495 0 Ignore 2100.0pF 0.5pF 0.0000 19168598 379774 0.9100 0.4900  

QPQ512
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ512 E4 T 5 5 100.0  

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1492 P_VDDQ_LGATE_20
5 1490 P_VDDQ_PHASE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3053 QPQ512_3_4 3000.0pF 3000.0pF 2 C 1492 1 0 Ignore 2100.0pF 6776.4pF 15.772 19.022 60.792 3900.0 2100.0  
3054 QPQ512_4_5_1 5.000V 0.300V 4 Q 1 1490 1492 0.390V Ignore 0.090V 0.0006 51.375 71.292 0.3900 0.2100  
3055 QPQ512_5_1(N) 0.700V 0.700V 0 Q 1490 1492 0 0.910V 0.490V 0.570V 0.0119 5.8870 2.1490 0.9100 0.4900  
3056 QPQ512_5_1(N) 3000.0pF 3000.0pF 2 C 1492 1490 0 Ignore 2100.0pF 0.6pF 0.0119 5.8870 2.1490 0.9100 0.4900  

QPQ514
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ514 F4 T 5 5 100.0  

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1492 P_VDDQ_LGATE_20
5 1490 P_VDDQ_PHASE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3062 QPQ514_3_4 3000.0pF 3000.0pF 2 C 1492 1 0 Ignore 2100.0pF 6747.8pF 36.282 8.2680 26.163 3900.0 2100.0  
3063 QPQ514_4_5_1 5.000V 0.300V 4 Q 1 1490 1492 0.390V Ignore 0.000V 0.0002 177.97 424.02 0.3900 0.2100  
3064 QPQ514_5_1(N) 0.700V 0.700V 0 Q 1490 1492 0 0.910V 0.490V 0.510V 0.0224 3.1190 0.3510 0.9100 0.4900  
3065 QPQ514_5_1(N) 3000.0pF 3000.0pF 2 C 1492 1490 0 Ignore 2100.0pF 0.5pF 0.0224 3.1190 0.3510 0.9100 0.4900  

QPQ515
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ515 D4 T 3 3 100.0  

Pin Nail Net Name
1 979 P_+VDDQ_PG_B1_10
2 1 GND
3 978 P_+VDDQ_PG_B2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3066 QPQ515_1_2 0.700V 0.700V 0 Q 979 1 0 0.910V 0.490V 0.790V 0.0000 11537800 6805577 0.9100 0.4900  
3067 QPQ515_2_3 1.500V 0.300V 4 Q 978 1 979 0.390V Ignore 0.140V 0.0002 177.97 136.88 0.3900 0.2100  
3068 QPQ515_3_1 0.700V 0.700V 0 Q 979 978 0 0.910V 0.490V 0.780V 0.0000 5883753 3634142 0.9100 0.4900  

QPQ516
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ516 D4 T 3 3 100.0  

Pin Nail Net Name
1 978 P_+VDDQ_PG_B2_10
2 1 GND
3 1551 P_+VDDQ_PG_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3069 QPQ516_1_2 3000.0pF 100.00pF 2 C 978 1 0 Ignore 70.00pF 102.22pF 1.5229 6.5660 6.0800 130.00 70.000  
3070 QPQ516_2_3_1 5.000V 0.300V 4 Q 1 1551 978 0.390V Ignore 0.030V 0.0002 177.97 357.43 0.3900 0.2100  
3071 QPQ516_3_1(N) 0.700V 0.700V 1 Q 1 1551 0 0.910V 0.490V 0.670V 0.0000 11856388 10290373 0.9100 0.4900  
3072 QPQ516_3_1(N) 3000.0pF 30.00pF 2 C 978 1551 0 Ignore 21.00pF 0.67pF 0.0000 11856388 10290373 0.9100 0.4900  

QPQ520
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ520 C4 T 3 3 100.0  

Pin Nail Net Name
1 920 P_DDR_VTT_C_10
2 1 GND
3 910 P_VTT_DDR_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3073 QPQ520_1_2 3000.0pF 100.00pF 2 C 920 1 0 Ignore 70.00pF 102.89pF 0.5014 19.945 18.026 130.00 70.000  
3074 QPQ520_2_3_1 5.000V 0.300V 4 Q 1 910 920 0.390V Ignore 0.030V 0.0002 177.97 355.31 0.3900 0.2100  
3075 QPQ520_3_1(N) 0.700V 0.700V 1 Q 1 910 0 0.910V 0.490V 0.710V 0.0000 7846841 7410450 0.9100 0.4900  
3076 QPQ520_3_1(N) 3000.0pF 30.00pF 2 C 920 910 0 Ignore 21.00pF 0.71pF 0.0000 7846841 7410450 0.9100 0.4900  

QPQ521
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ521 C4 T 3 3 100.0  

Pin Nail Net Name
1 922 DDR_VTT_CNTL_B_10
2 1 GND
3 920 P_DDR_VTT_C_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3077 QPQ521_1_2 0.700V 0.700V 0 Q 922 1 0 0.910V 0.490V 0.790V 0.0000 7047291 4107857 0.9100 0.4900  
3078 QPQ521_2_3 1.500V 0.300V 4 Q 920 1 922 0.390V Ignore 0.110V 0.0002 177.97 199.43 0.3900 0.2100  
3079 QPQ521_3_1 0.700V 0.700V 0 Q 922 920 0 0.910V 0.490V 0.780V 0.0000 10129079 6185884 0.9100 0.4900  

QPQ522
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ522 F4 T 3 3 100.0  

Pin Nail Net Name
1 1508 P_VDDQ_COMP_GATE_10
2 1 GND
3 1507 P_VDDQ_COMP_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3080 QPQ522_1_2 3000.0pF 60.00pF 2 C 1508 1 0 Ignore 42.00pF 65.17pF 1.7320 3.4640 2.4680 78.000 42.000  
3081 QPQ522_2_3_1 5.000V 0.700V 4 Q 1 1507 1508 0.910V Ignore 0.020V 0.0002 415.26 925.54 0.9100 0.4900  
3082 QPQ522_3_1(N) 0.700V 0.700V 0 Q 1 1507 0 0.910V 0.490V 0.590V 0.0008 83.052 41.098 0.9100 0.4900  
3083 QPQ522_3_1(N) 3000.0pF 50.00pF 2 C 1508 1507 0 Ignore 35.00pF 0.59pF 0.0008 83.052 41.098 0.9100 0.4900  

QPQ523
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ523 F4 T 3 3 100.0  

Pin Nail Net Name
1 1506 P_+5V_R1_10
2 1505 P_+VDDQ_C1_10
3 1508 P_VDDQ_COMP_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3084 QPQ523_1_2 0.700V 0.700V 0 Q 1506 1505 0 0.910V 0.490V 0.790V 0.0000 11537800 6805577 0.9100 0.4900  
3085 QPQ523_2_3 1.500V 0.300V 4 Q 1508 1505 1506 0.390V Ignore 0.110V 0.0000 27687868 29439412 0.3900 0.2100  
3086 QPQ523_3_1 0.700V 0.700V 0 Q 1506 1508 0 0.910V 0.490V 0.780V 0.0000 5883753 3634142 0.9100 0.4900  

QPQ532
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ532 E4 T 3 3 100.0  

Pin Nail Net Name
1 675 S_SLP_S4_
2 1 GND
3 1487 P_+VDDQ_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3087 QPQ532_1_2 3000.0pF 1000.0pF 2 C 675 1 0 Ignore 700.0pF 1190.9pF 6.5456 15.277 5.5560 1300.0 700.00  
3088 QPQ532_2_3_1 5.000V 0.700V 4 Q 1 1487 675 0.910V Ignore 0.460V 0.0002 415.26 54.319 0.9100 0.4900  
3089 QPQ532_3_1(N) 0.700V 0.700V 0 Q 1 1487 0 0.910V 0.490V 0.620V 0.0008 83.052 52.260 0.9100 0.4900  
3090 QPQ532_3_1(N) 3000.0pF 30.00pF 2 C 675 1487 0 Ignore 21.00pF 0.62pF 0.0008 83.052 52.260 0.9100 0.4900  

QPQ533
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ533 E4 T 3 3 100.0  

Pin Nail Net Name
1 1487 P_+VDDQ_G_10
2 1 GND
3 1488 P_+VDDQ_S

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3091 QPQ533_1_2 3000.0pF 3000.0pF 2 C 1487 1 0 Ignore 2100.0pF 5300.2pF 10.305 29.111 45.291 3900.0 2100.0  
3092 QPQ533_2_3_1 5.000V 0.700V 4 Q 1 1488 1487 0.910V Ignore 0.000V 0.0002 415.26 963.07 0.9100 0.4900  
3093 QPQ533_3_1(N) 0.700V 0.600V 1 Q 1 1488 0 0.780V 0.420V 0.490V 0.0000 8463914 3075290 0.7800 0.4200  
3094 QPQ533_3_1(N) 3000.0pF 1200.0pF 2 C 1487 1488 0 Ignore 840.0pF 0.5pF 0.0000 8463914 3075290 0.7800 0.4200  

QPQ601
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ601 C4 T 3 3 100.0  

Pin Nail Net Name
1 947 P_+5VSB_ATX_OV_B_10
2 970 +5VSB_ATX
3 946 P_5VSB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3095 QPQ601_1_2 0.700V 0.700V 0 Q 970 947 0 0.910V 0.490V 0.790V 0.0000 4838469 2719431 0.9100 0.4900  
3096 QPQ601_2_3 1.500V 0.300V 3 Q 946 970 947 0.390V Ignore 0.140V 0.0002 177.97 143.42 0.3900 0.2100  
3097 QPQ601_3_1 0.700V 0.700V 0 Q 946 947 0 0.910V 0.490V 0.790V 0.0008 83.052 49.181 0.9100 0.4900  

QPQ602
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ602 B4 T 3 3 100.0  

Pin Nail Net Name
1 393 P_+5VSB_ATX_OV_REF_10
2 394 P_+5VSB_ATX_OV_E_10
3 952 P_+5VSB_ATX_OV_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3098 QPQ602_1_2 0.700V 0.700V 0 Q 393 394 0 0.910V 0.490V 0.780V 0.0000 6787477 4050781 0.9100 0.4900  
3099 QPQ602_2_3 3.000V 0.300V 4 Q 952 394 393 0.390V Ignore 0.100V 0.0002 177.97 211.36 0.3900 0.2100  
3100 QPQ602_3_1 0.700V 0.700V 0 Q 393 952 0 0.910V 0.490V 0.780V 0.0000 5472657 3418270 0.9100 0.4900  

QPQ603
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ603 B4 T 3 3 100.0  

Pin Nail Net Name
1 401 P_5VSB_Q1_10
2 423 +5VSB
3 405 P_5VSB_SHORT_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3101 QPQ603_1_2 0.700V 0.700V 0 Q 401 423 0 0.910V 0.490V 0.780V 0.0000 6787477 4050781 0.9100 0.4900  
3102 QPQ603_2_3 3.000V 0.300V 4 Q 405 423 401 0.390V Ignore 0.100V 0.0002 177.97 217.32 0.3900 0.2100  
3103 QPQ603_3_1 0.700V 0.700V 0 Q 401 405 0 0.910V 0.490V 0.780V 0.0000 5472657 3418270 0.9100 0.4900  

QPQ604
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ604 B4 T 3 3 100.0  

Pin Nail Net Name
1 400 P_5VSB_Q3_10
2 1 GND
3 412 P_5VSB_GATE_10_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3104 QPQ604_1_2 0.700V 0.700V 0 Q 400 1 0 0.910V 0.490V 0.780V 0.0000 6787477 4050781 0.9100 0.4900  
3105 QPQ604_2_3 3.000V 0.300V 4 Q 412 1 400 0.390V Ignore 0.090V 0.0002 177.97 234.65 0.3900 0.2100  
3106 QPQ604_3_1 0.700V 0.700V 0 Q 400 412 0 0.910V 0.490V 0.780V 0.0000 5472657 3418270 0.9100 0.4900  

QPQ605
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ605 C4 T 3 3 100.0  

Pin Nail Net Name
1 946 P_5VSB_GATE_10
2 423 +5VSB
3 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3107 QPQ605_1_2 3000.0pF 1500.0pF 2 C 946 423 0 Ignore 1050.0pF 1982.1pF 66.534 2.2540 0.1610 1950.0 1050.0  
3108 QPQ605_2_3_1 5.000V 0.700V 3 Q 423 970 946 0.910V Ignore 0.420V 0.0006 119.88 41.792 0.9100 0.4900  
3109 QPQ605_3_1(P) 0.700V 0.700V 1 Q 423 970 0 0.910V 0.490V 0.620V 0.0000 10072077 6361128 0.9100 0.4900  
3110 QPQ605_3_1(P) 3000.0pF 1500.0pF 2 C 946 970 0 Ignore 1050.0pF 0.6pF 0.0000 10072077 6361128 0.9100 0.4900  

QPQ606
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ606 C4 T 5 5 100.0  

Pin Nail Net Name
1 3 +5V
2 3 +5V
3 3 +5V
4 404 P_5VSB_GATE1_10
5 423 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3111 QPQ606_3_4 3000.0pF 3000.0pF 2 C 404 3 0 Ignore 2100.0pF 3021.9pF 42.135 7.1200 6.9460 3900.0 2100.0  
3112 QPQ606_4_5_1 5.000V 0.300V 4 Q 3 423 404 0.390V Ignore 0.000V 0.0000 -1531758848 2085287936 0.3900 0.2100  
3113 QPQ606_5_1(N) 0.700V 0.700V 1 Q 3 423 0 0.910V 0.490V 0.650V 0.0000 12212978 9156550 0.9100 0.4900  
3114 QPQ606_5_1(N) 3000.0pF 3000.0pF 2 C 404 423 0 Ignore 2100.0pF 0.6pF 0.0000 12212978 9156550 0.9100 0.4900  

QPQ607
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ607 B4 T 3 3 100.0  

Pin Nail Net Name
1 406 P_5VSB_Q2_10
2 1 GND
3 404 P_5VSB_GATE1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3115 QPQ607_1_2 0.700V 0.700V 0 Q 406 1 0 0.910V 0.490V 0.780V 0.0000 6787477 4050781 0.9100 0.4900  
3116 QPQ607_2_3 3.000V 0.300V 4 Q 404 1 406 0.390V Ignore 0.090V 0.0002 177.97 230.03 0.3900 0.2100  
3117 QPQ607_3_1 0.700V 0.700V 0 Q 406 404 0 0.910V 0.490V 0.780V 0.0000 5472657 3418270 0.9100 0.4900  

QPQ608
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ608 D4 T 3 3 100.0  

Pin Nail Net Name
1 981 P_5V_USB_Q3_10
2 1 GND
3 362 P_5VSB_USB_GATE_10_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3118 QPQ608_1_2 0.700V 0.700V 0 Q 981 1 0 0.910V 0.490V 0.780V 0.0000 6614434 3993490 0.9100 0.4900  
3119 QPQ608_2_3 3.000V 0.300V 4 Q 362 1 981 0.390V Ignore 0.100V 0.0002 177.97 225.41 0.3900 0.2100  
3120 QPQ608_3_1 0.700V 0.700V 0 Q 981 362 0 0.910V 0.490V 0.780V 0.0000 5472657 3418270 0.9100 0.4900  

QPQ609
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ609 D4 T 3 3 100.0  

Pin Nail Net Name
1 980 P_5V_USB_Q2_10
2 1 GND
3 1489 P_5V_USB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3121 QPQ609_1_2 0.700V 0.700V 0 Q 980 1 0 0.910V 0.490V 0.780V 0.0008 83.052 49.758 0.9100 0.4900  
3122 QPQ609_2_3 3.000V 0.300V 4 Q 1489 1 980 0.390V Ignore 0.090V 0.0002 177.97 229.45 0.3900 0.2100  
3123 QPQ609_3_1 0.700V 0.700V 0 Q 980 1489 0 0.910V 0.490V 0.780V 0.0000 5472657 3418270 0.9100 0.4900  

QPQ610
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ610 F4 T 5 5 100.0  

Pin Nail Net Name
1 3 +5V
2 3 +5V
3 3 +5V
4 1489 P_5V_USB_GATE_10
5 1229 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3124 QPQ610_3_4 3000.0pF 4000.0pF 2 C 1489 3 0 Ignore 2800.0pF 3812.2pF 13.319 30.031 25.331 5200.0 2800.0  
3125 QPQ610_4_5_1 5.000V 0.300V 4 Q 3 1229 1489 0.390V Ignore 0.000V 0.0002 177.97 408.81 0.3900 0.2100  
3126 QPQ610_5_1(N) 0.700V 0.700V 1 Q 3 1229 0 0.910V 0.490V 0.630V 0.0008 83.052 56.301 0.9100 0.4900  
3127 QPQ610_5_1(N) 3000.0pF 4000.0pF 2 C 1489 1229 0 Ignore 2800.0pF 0.6pF 0.0008 83.052 56.301 0.9100 0.4900  

QPQ611
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ611 D4 T 3 3 100.0  

Pin Nail Net Name
1 966 P_5VSB_USB_GATE_10
2 1229 +5VSB_DUAL
3 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3128 QPQ611_1_2 3000.0pF 3000.0pF 2 C 966 1229 0 Ignore 2100.0pF 7266.0pF 86.803 3.4560 12.926 3900.0 2100.0  
3129 QPQ611_2_3_1 5.000V 0.700V 3 Q 1229 970 966 0.910V Ignore 0.040V 0.0002 415.26 899.17 0.9100 0.4900  
3130 QPQ611_3_1(P) 0.700V 0.700V 1 Q 1229 970 0 0.910V 0.490V 0.620V 0.0008 83.052 53.222 0.9100 0.4900  
3131 QPQ611_3_1(P) 3000.0pF 3000.0pF 2 C 966 970 0 Ignore 2100.0pF 0.6pF 0.0008 83.052 53.222 0.9100 0.4900  

QPQ612
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ612 E4 T 3 3 100.0  

Pin Nail Net Name
1 971 P_5V_USB_Q1_10
2 1229 +5VSB_DUAL
3 1486 P_5VSB_DUAL_SHORT_10_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3132 QPQ612_1_2 0.700V 0.700V 0 Q 971 1229 0 0.910V 0.490V 0.780V 0.0000 5472657 3418270 0.9100 0.4900  
3133 QPQ612_2_3 3.000V 0.300V 4 Q 1486 1229 971 0.390V Ignore 0.130V 0.0003 102.75 87.250 0.3900 0.2100  
3134 QPQ612_3_1 0.700V 0.700V 0 Q 971 1486 0 0.910V 0.490V 0.780V 0.0000 15525381 9805219 0.9100 0.4900  

QPQ613
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ613 B4 T 3 3 100.0  

Pin Nail Net Name
1 403 P_5VSB_B1_10
2 1 GND
3 401 P_5VSB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3135 QPQ613_1_2 0.700V 0.700V 0 Q 403 1 0 0.910V 0.490V 0.790V 0.0008 83.052 48.796 0.9100 0.4900  
3136 QPQ613_2_3 1.500V 0.300V 4 Q 401 1 403 0.390V Ignore 0.160V 0.0002 177.97 97.813 0.3900 0.2100  
3137 QPQ613_3_1 0.700V 0.700V 0 Q 403 401 0 0.910V 0.490V 0.780V 0.0008 83.052 50.913 0.9100 0.4900  

QPQ614
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ614 D4 T 3 3 100.0  

Pin Nail Net Name
1 973 P_+5VSB_DUAL_OV_B_10
2 970 +5VSB_ATX
3 966 P_5VSB_USB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3138 QPQ614_1_2 0.700V 0.700V 0 Q 970 973 0 0.910V 0.490V 0.790V 0.0000 19824122 11279835 0.9100 0.4900  
3139 QPQ614_2_3 1.500V 0.300V 3 Q 966 970 973 0.390V Ignore 0.140V 0.0002 177.97 145.73 0.3900 0.2100  
3140 QPQ614_3_1 0.700V 0.700V 0 Q 966 973 0 0.910V 0.490V 0.780V 0.0000 6787477 4050781 0.9100 0.4900  

QPQ615
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ615 D4 T 3 3 100.0  

Pin Nail Net Name
1 977 P_+5VSB_DUAL_OV_REF_10
2 974 P_+5VSB_DUAL_OV_E_10
3 975 P_+5VSB_DUAL_OV_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3141 QPQ615_1_2 0.700V 0.700V 0 Q 977 974 0 0.910V 0.490V 0.780V 0.0008 83.052 49.950 0.9100 0.4900  
3142 QPQ615_2_3 3.000V 0.300V 4 Q 975 974 977 0.390V Ignore 0.100V 0.0002 177.97 219.06 0.3900 0.2100  
3143 QPQ615_3_1 0.700V 0.700V 0 Q 977 975 0 0.910V 0.490V 0.780V 0.0008 83.052 52.260 0.9100 0.4900  

QPQ620
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ620 B4 T 3 3 100.0  

Pin Nail Net Name
1 650 O_DEEP_S5
2 1 GND
3 401 P_5VSB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3144 QPQ620_1_2 3000.0pF 3000.0pF 2 C 650 1 0 Ignore 2100.0pF 2600.7pF 52.707 5.6920 3.1670 3900.0 2100.0  
3145 QPQ620_2_3_1 5.000V 0.700V 4 Q 1 401 650 0.910V Ignore 0.220V 0.0002 415.26 525.44 0.9100 0.4900  
3146 QPQ620_3_1(N) 0.700V 0.700V 0 Q 1 401 0 0.910V 0.490V 0.600V 0.0000 6630501 3450073 0.9100 0.4900  
3147 QPQ620_3_1(N) 3000.0pF 1070.0pF 1 C 650 401 0 Ignore 749.0pF 0.6pF 0.0000 6630501 3450073 0.9100 0.4900  

QPQ621
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ621 B4 T 3 3 100.0  

Pin Nail Net Name
1 410 P_5VSB_GATE_B1_10
2 408 P_5VSB_GATE_R_10
3 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3148 QPQ621_1_2 0.700V 0.700V 0 Q 410 408 0 0.910V 0.490V 0.790V 0.0008 83.052 48.026 0.9100 0.4900  
3149 QPQ621_2_3 1.500V 0.300V 4 Q 970 408 410 0.390V Ignore 0.110V 0.0000 27239530 30288238 0.3900 0.2100  
3150 QPQ621_3_1 0.700V 0.700V 0 Q 410 970 0 0.910V 0.490V 0.780V 0.0000 10129079 6185884 0.9100 0.4900  

QPQ622
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ622 B4 T 3 3 100.0  

Pin Nail Net Name
1 411 P_SLPS3__C1_10
2 1 GND
3 409 P_5VSB_GATE_RC_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3151 QPQ622_1_2 0.700V 0.700V 0 Q 411 1 0 0.910V 0.490V 0.790V 0.0000 11537800 6805577 0.9100 0.4900  
3152 QPQ622_2_3 3.000V 0.300V 4 Q 409 1 411 0.390V Ignore 0.080V 0.0002 177.97 248.50 0.3900 0.2100  
3153 QPQ622_3_1 0.700V 0.700V 0 Q 411 409 0 0.910V 0.490V 0.780V 0.0008 83.052 51.490 0.9100 0.4900  

QPQ624
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ624 B4 T 3 3 100.0  

Pin Nail Net Name
1 407 P_SLPS3__R_10
2 1 GND
3 411 P_SLPS3__C1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3154 QPQ624_1_2 0.700V 0.700V 0 Q 407 1 0 0.910V 0.490V 0.790V 0.0000 7047291 4107857 0.9100 0.4900  
3155 QPQ624_2_3 1.500V 0.300V 4 Q 411 1 407 0.390V Ignore 0.120V 0.0002 177.97 178.64 0.3900 0.2100  
3156 QPQ624_3_1 0.700V 0.700V 0 Q 407 411 0 0.910V 0.490V 0.780V 0.0000 10129079 6185884 0.9100 0.4900  

QPQ625
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ625 B4 T 3 3 100.0  

Pin Nail Net Name
1 200 S_PWROK
2 1 GND
3 407 P_SLPS3__R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3157 QPQ625_1_2 3000.0pF 1200.0pF 2 C 200 1 0 Ignore 840.0pF 1290.6pF 15.551 7.7160 5.7760 1560.0 840.00  
3158 QPQ625_2_3_1 5.000V 0.700V 4 Q 1 407 200 0.910V Ignore 0.480V 0.0002 415.26 11.210 0.9100 0.4900  
3159 QPQ625_3_1(N) 0.700V 0.700V 0 Q 1 407 0 0.910V 0.490V 0.610V 0.0000 53147508 29501764 0.9100 0.4900  
3160 QPQ625_3_1(N) 3000.0pF 165.00pF 2 C 200 407 0 Ignore 115.50pF 0.61pF 0.0000 53147508 29501764 0.9100 0.4900  

QPQ704
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ704 C4 T 3 3 100.0  

Pin Nail Net Name
1 921 P_VDDQ_B1_10
2 1 GND
3 911 P_VDDQ_G1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3161 QPQ704_1_2 0.700V 0.700V 0 Q 921 1 0 0.910V 0.490V 0.780V 0.0000 5017070 3203461 0.9100 0.4900  
3162 QPQ704_2_3 5.000V 0.300V 4 Q 911 1 921 0.390V Ignore 0.140V 0.0000 25948820 19340606 0.3900 0.2100  
3163 QPQ704_3_1 0.700V 0.700V 0 Q 921 911 0 0.910V 0.490V 0.770V 0.0008 83.052 54.954 0.9100 0.4900  

QPQ705
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ705 B4 T 3 3 100.0  

Pin Nail Net Name
1 446 P_VCCST_VCCSFR_B_10
2 1 GND
3 445 P_VCCST_VCCSFR_C_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3164 QPQ705_1_2 0.700V 0.700V 0 Q 446 1 0 0.910V 0.490V 0.790V 0.0000 7047291 4107857 0.9100 0.4900  
3165 QPQ705_2_3 1.500V 0.300V 4 Q 445 1 446 0.390V Ignore 0.120V 0.0002 177.97 183.07 0.3900 0.2100  
3166 QPQ705_3_1 0.700V 0.700V 0 Q 446 445 0 0.910V 0.490V 0.780V 0.0008 83.052 50.913 0.9100 0.4900  

QPQ706
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ706 B4 T 3 3 100.0  

Pin Nail Net Name
1 445 P_VCCST_VCCSFR_C_10
2 1 GND
3 444 P_VCCST_VCCSFR_D1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3167 QPQ706_1_2 3000.0pF 60.00pF 2 C 445 1 0 Ignore 42.00pF 70.63pF 1.8268 3.2840 1.3450 78.000 42.000  
3168 QPQ706_2_3_1 5.000V 0.700V 4 Q 1 444 445 0.910V Ignore 0.020V 0.0002 415.26 925.73 0.9100 0.4900  
3169 QPQ706_3_1(N) 0.700V 0.700V 0 Q 1 444 0 0.910V 0.490V 0.610V 0.0000 8250093 4522210 0.9100 0.4900  
3170 QPQ706_3_1(N) 3000.0pF 80.00pF 2 C 445 444 0 Ignore 56.00pF 0.61pF 0.0000 8250093 4522210 0.9100 0.4900  

QPQ707
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ707 D1 T 3 3 100.0  

Pin Nail Net Name
1 1223 P_VCCSA_B1_10
2 1 GND
3 1228 P_VCCSA_C1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3171 QPQ707_1_2 0.700V 0.700V 0 Q 1223 1 0 0.910V 0.490V 0.780V 0.0000 6614434 3993490 0.9100 0.4900  
3172 QPQ707_2_3 3.000V 0.300V 4 Q 1228 1 1223 0.390V Ignore 0.130V 0.0002 177.97 161.13 0.3900 0.2100  
3173 QPQ707_3_1 0.700V 0.700V 0 Q 1223 1228 0 0.910V 0.490V 0.780V 0.0008 83.052 52.260 0.9100 0.4900  

QPQ708
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ708 C4 T 3 3 100.0  

Pin Nail Net Name
1 911 P_VDDQ_G1_10
2 423 +5VSB
3 422 +5VDUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3174 QPQ708_1_2 3000.0pF 2000.0pF 2 C 911 423 0 Ignore 1400.0pF 2375.7pF 35.125 5.6940 2.1290 2600.0 1400.0  
3175 QPQ708_2_3_1 5.000V 0.300V 3 Q 423 422 911 0.390V Ignore 0.070V 0.0000 50478112 77088632 0.3900 0.2100  
3176 QPQ708_3_1(P) 0.700V 0.700V 0 Q 423 422 0 0.910V 0.490V 0.620V 0.0008 83.052 52.645 0.9100 0.4900  
3177 QPQ708_3_1(P) 3000.0pF 1000.0pF 2 C 911 422 0 Ignore 700.0pF 0.6pF 0.0008 83.052 52.645 0.9100 0.4900  

QPQ709
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ709 B4 T 3 3 100.0  

Pin Nail Net Name
1 444 P_VCCST_VCCSFR_D1_10
2 842 VCCST_VCCSFR
3 501 +1_0V_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3178 QPQ709_1_2 3000.0pF 1500.0pF 2 C 444 842 0 Ignore 1050.0pF 1398.0pF 14.441 10.387 8.0330 1950.0 1050.0  
3179 QPQ709_2_3_1 5.000V 0.300V 4 Q 842 501 444 0.390V Ignore 0.020V 0.0007 44.492 93.687 0.3900 0.2100  
3180 QPQ709_3_1(N) 0.700V 0.700V 0 Q 501 444 0 0.910V 0.490V 0.620V 0.0000 6742946 4117955 0.9100 0.4900  
3181 QPQ709_3_1(N) 3000.0pF 1500.0pF 2 C 444 501 0 Ignore 1050.0pF 0.6pF 0.0000 6742946 4117955 0.9100 0.4900  

QPQ710
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ710 D1 T 5 5 100.0  

Pin Nail Net Name
1 1198 P_VCCSA_PHASE_20
2 1198 P_VCCSA_PHASE_20
3 1198 P_VCCSA_PHASE_20
4 1201 P_VCCSA_UGATE_M_20
5 1316 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3182 QPQ710_3_4 3000.0pF 3000.0pF 2 C 1201 1198 0 Ignore 2100.0pF 3714.8pF 23.686 12.666 2.6070 3900.0 2100.0  
3183 QPQ710_4_5_1 5.000V 0.300V 4 Q 1198 1316 1201 0.390V Ignore -0.090V 0.0072 4.1870 14.126 0.3900 0.2100  
3184 QPQ710_5_1(N) 0.700V 0.700V 0 Q 1316 1201 0 0.910V 0.490V 0.510V 0.0061 11.517 0.8420 0.9100 0.4900  
3185 QPQ710_5_1(N) 3000.0pF 3000.0pF 2 C 1201 1316 0 Ignore 2100.0pF 0.5pF 0.0061 11.517 0.8420 0.9100 0.4900  

QPQ711
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ711 D2 T 5 5 100.0  

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1206 P_VCCSA_LGATE_20
5 1198 P_VCCSA_PHASE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3186 QPQ711_3_4 3000.0pF 3000.0pF 2 C 1206 1 0 Ignore 2100.0pF 3324.5pF 42.002 7.1430 4.5670 3900.0 2100.0  
3187 QPQ711_4_5_1 5.000V 0.300V 4 Q 1 1198 1206 0.390V Ignore 0.060V 0.0057 5.2280 8.9730 0.3900 0.2100  
3188 QPQ711_5_1(N) 0.700V 0.700V 0 Q 1198 1206 0 0.910V 0.490V 0.610V 0.0055 12.665 7.0890 0.9100 0.4900  
3189 QPQ711_5_1(N) 3000.0pF 3000.0pF 2 C 1206 1198 0 Ignore 2100.0pF 0.6pF 0.0055 12.665 7.0890 0.9100 0.4900  

QPQ712
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ712 D1 T 3 3 100.0  

Pin Nail Net Name
1 1228 P_VCCSA_C1_10
2 1 GND
3 1222 P_VCCSA_COMP_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3190 QPQ712_1_2 3000.0pF 100.00pF 2 C 1228 1 0 Ignore 70.00pF 106.06pF 0.4300 23.257 18.563 130.00 70.000  
3191 QPQ712_2_3_1 5.000V 0.700V 4 Q 1 1222 1228 0.910V Ignore 0.030V 0.0002 415.26 903.22 0.9100 0.4900  
3192 QPQ712_3_1(N) 0.700V 0.700V 0 Q 1 1222 0 0.910V 0.490V 0.600V 0.0000 16450710 8674220 0.9100 0.4900  
3193 QPQ712_3_1(N) 3000.0pF 30.00pF 2 C 1228 1222 0 Ignore 21.00pF 0.60pF 0.0000 16450710 8674220 0.9100 0.4900  

QPQ801
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ801 F3 T 3 3 100.0  

Pin Nail Net Name
1 1587 P_VREN__10
2 1 GND
3 1225 P_VCORE_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3209 QPQ801_1_2 3000.0pF 1200.0pF 2 C 1587 1 0 Ignore 840.0pF 1283.5pF 17.224 6.9670 5.3510 1560.0 840.00  
3210 QPQ801_2_3_1 5.000V 0.700V 4 Q 1 1225 1587 0.910V Ignore 0.050V 0.0002 415.26 863.96 0.9100 0.4900  
3211 QPQ801_3_1(N) 0.700V 0.700V 0 Q 1 1225 0 0.910V 0.490V 0.560V 0.0000 8391893 2849802 0.9100 0.4900  
3212 QPQ801_3_1(N) 3000.0pF 200.00pF 2 C 1587 1225 0 Ignore 140.00pF 0.56pF 0.0000 8391893 2849802 0.9100 0.4900  

QPQ803
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ803 F3 T 3 3 100.0  

Pin Nail Net Name
1 1588 P_VREN_10
2 1 GND
3 1587 P_VREN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3213 QPQ803_1_2 3000.0pF 100.00pF 2 C 1588 1 0 Ignore 70.00pF 88.69pF 3.2509 3.0760 1.9170 130.00 70.000  
3214 QPQ803_2_3_1 5.000V 0.700V 4 Q 1 1587 1588 0.910V Ignore 0.020V 0.0002 415.26 921.50 0.9100 0.4900  
3215 QPQ803_3_1(N) 0.700V 0.700V 0 Q 1 1587 0 0.910V 0.490V 0.620V 0.0008 83.052 50.528 0.9100 0.4900  
3216 QPQ803_3_1(N) 3000.0pF 50.00pF 2 C 1588 1587 0 Ignore 35.00pF 0.62pF 0.0008 83.052 50.528 0.9100 0.4900  

QPQ805
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ805 F3 T 3 3 100.0  

Pin Nail Net Name
1 1587 P_VREN__10
2 1 GND
3 373 P_VR_READY_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3217 QPQ805_1_2 3000.0pF 1200.0pF 2 C 1587 1 0 Ignore 840.0pF 1263.5pF 68.405 1.7540 1.4450 1560.0 840.00  
3218 QPQ805_2_3_1 5.000V 0.700V 4 Q 1 373 1587 0.910V Ignore 0.050V 0.0000 207005072 430774912 0.9100 0.4900  
3219 QPQ805_3_1(N) 0.700V 0.700V 0 Q 1 373 0 0.910V 0.490V 0.560V 0.0000 7235601 2507436 0.9100 0.4900  
3220 QPQ805_3_1(N) 3000.0pF 20.00pF 2 C 1587 373 0 Ignore 14.00pF 0.56pF 0.0000 7235601 2507436 0.9100 0.4900  

QPQ806
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ806 F3 T 3 3 100.0  

Pin Nail Net Name
1 1585 P_+12V_3V_EN_C1_10
2 1 GND
3 1582 P_+12V_3V_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3221 QPQ806_1_2 3000.0pF 50.00pF 2 C 1585 1 0 Ignore 35.00pF 72.46pF 2.9030 1.7220 0.8560 65.000 35.000  
3222 QPQ806_2_3_1 5.000V 0.700V 4 Q 1 1582 1585 0.910V Ignore 0.020V 0.0002 415.26 925.73 0.9100 0.4900  
3223 QPQ806_3_1(N) 0.700V 0.700V 1 Q 1 1582 0 0.910V 0.490V 0.660V 0.0000 21641096 17278276 0.9100 0.4900  
3224 QPQ806_3_1(N) 3000.0pF 30.00pF 2 C 1585 1582 0 Ignore 21.00pF 0.66pF 0.0000 21641096 17278276 0.9100 0.4900  

QPQ807
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ807 F3 T 3 3 100.0  

Pin Nail Net Name
1 1584 P_+12V_3V_EN_B1_10
2 1595 P_+12V_3V_EN_C2_10
3 1585 P_+12V_3V_EN_C1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3225 QPQ807_1_2 0.700V 0.700V 0 Q 1584 1595 0 0.910V 0.490V 0.790V 0.0008 83.052 48.603 0.9100 0.4900  
3226 QPQ807_2_3 1.500V 0.300V 4 Q 1585 1595 1584 0.390V Ignore 0.110V 0.0000 420819136 450170720 0.3900 0.2100  
3227 QPQ807_3_1 0.700V 0.700V 0 Q 1584 1585 0 0.910V 0.490V 0.780V 0.0008 83.052 51.105 0.9100 0.4900  

QPQ808
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ808 F4 T 3 3 100.0  

Pin Nail Net Name
1 1550 P_VRM_PGD_10
2 1 GND
3 1549 P_VCORE_PG__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3228 QPQ808_1_2 0.700V 0.700V 0 Q 1550 1 0 0.910V 0.490V 0.780V 0.0000 10129079 6185884 0.9100 0.4900  
3229 QPQ808_2_3 3.000V 0.300V 4 Q 1549 1 1550 0.390V Ignore 0.140V 0.0003 88.984 70.557 0.3900 0.2100  
3230 QPQ808_3_1 0.700V 0.700V 0 Q 1550 1549 0 0.910V 0.490V 0.780V 0.0000 5017070 3203461 0.9100 0.4900  

QPQ809
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ809 F4 T 3 3 100.0  

Pin Nail Net Name
1 1549 P_VCORE_PG__10
2 1 GND
3 373 P_VR_READY_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3231 QPQ809_1_2 3000.0pF 100.00pF 2 C 1549 1 0 Ignore 70.00pF 111.81pF 1.4302 6.9920 4.2390 130.00 70.000  
3232 QPQ809_2_3_1 5.000V 0.700V 4 Q 1 373 1549 0.910V Ignore 0.040V 0.0000 276576448 599008640 0.9100 0.4900  
3233 QPQ809_3_1(N) 0.700V 0.700V 0 Q 1 373 0 0.910V 0.490V 0.560V 0.0008 83.052 28.973 0.9100 0.4900  
3234 QPQ809_3_1(N) 3000.0pF 330.00pF 1 C 1549 373 0 Ignore 231.00pF 0.56pF 0.0008 83.052 28.973 0.9100 0.4900  

QPQ810
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ810 F3 T 3 3 100.0  

Pin Nail Net Name
1 1596 P_+12V_3V_EN_B2_10
2 1 GND
3 1595 P_+12V_3V_EN_C2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3235 QPQ810_1_2 0.700V 0.700V 0 Q 1596 1 0 0.910V 0.490V 0.790V 0.0000 11537800 6805577 0.9100 0.4900  
3236 QPQ810_2_3 1.500V 0.300V 4 Q 1595 1 1596 0.390V Ignore 0.130V 0.0002 177.97 149.77 0.3900 0.2100  
3237 QPQ810_3_1 0.700V 0.700V 0 Q 1596 1595 0 0.910V 0.490V 0.780V 0.0000 5883753 3634142 0.9100 0.4900  

QPQ811
Device Loc Side Total Pin Tested Coverage (%) Comment
QPQ811 F3 T 3 3 100.0  

Pin Nail Net Name
1 1587 P_VREN__10
2 1 GND
3 1203 P_+VCCIO_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3238 QPQ811_1_2 3000.0pF 1200.0pF 2 C 1587 1 0 Ignore 840.0pF 1264.8pF 36.708 3.2690 2.6810 1560.0 840.00  
3239 QPQ811_2_3_1 5.000V 0.300V 4 Q 1 1203 1587 0.390V Ignore 0.050V 0.0002 177.97 312.01 0.3900 0.2100  
3240 QPQ811_3_1(N) 0.700V 0.700V 0 Q 1 1203 0 0.910V 0.490V 0.550V 0.0008 83.052 22.238 0.9100 0.4900  
3241 QPQ811_3_1(N) 3000.0pF 30.00pF 2 C 1587 1203 0 Ignore 21.00pF 0.55pF 0.0008 83.052 22.238 0.9100 0.4900  

QPU702
Device Loc Side Total Pin Tested Coverage (%) Comment
QPU702 A1 T 3 3 100.0  

Pin Nail Net Name
1 81 P_+3VSB_ATX_ADJ_20
2 706 +3VSB_ATX
3 970 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3245 QPU702_1_2 0.700V 0.700V 0 Q 81 706 0 0.910V 0.490V 0.760V 0.0000 7476578 5293635 0.9100 0.4900  
3246 QPU702_2_3 0.700V 0.700V 1 Q 706 970 0 0.910V 0.490V 0.700V 0.0000 9273775 9209306 0.9100 0.4900  
3247 QPU702_3_1 1.300V 1.300V 0 Q 81 970 0 1.690V 0.910V 1.340V 0.0000 9316119 8374567 1.6900 0.9100  

QQSWQ2
Device Loc Side Total Pin Tested Coverage (%) Comment
QQSWQ2 B4 T 3 3 100.0  

Pin Nail Net Name
1 461 GPP_G1
2 1 GND
3 438 P_+1_0V_A_OV2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3248 QQSWQ2_1_2 3000.0pF 100.00pF 2 C 461 1 0 Ignore 70.00pF 118.86pF 2.6548 3.7670 1.3990 130.00 70.000  
3249 QQSWQ2_2_3_1 5.000V 0.700V 4 Q 1 438 461 0.910V Ignore 0.460V 0.0002 415.26 54.896 0.9100 0.4900  
3250 QQSWQ2_3_1(N) 0.700V 0.700V 0 Q 1 438 0 0.910V 0.490V 0.610V 0.0000 6358021 3573487 0.9100 0.4900  
3251 QQSWQ2_3_1(N) 3000.0pF 30.00pF 2 C 461 438 0 Ignore 21.00pF 0.61pF 0.0000 6358021 3573487 0.9100 0.4900  

QQSWQ3
Device Loc Side Total Pin Tested Coverage (%) Comment
QQSWQ3 B4 T 3 3 100.0  

Pin Nail Net Name
1 462 GPP_G0
2 1 GND
3 437 P_+1_0V_A_OV1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3252 QQSWQ3_1_2 3000.0pF 100.00pF 2 C 462 1 0 Ignore 70.00pF 121.26pF 1.9309 5.1790 1.5090 130.00 70.000  
3253 QQSWQ3_2_3_1 5.000V 0.700V 4 Q 1 437 462 0.910V Ignore 0.430V 0.0002 415.26 111.09 0.9100 0.4900  
3254 QQSWQ3_3_1(N) 0.700V 0.700V 0 Q 1 437 0 0.910V 0.490V 0.610V 0.0008 83.052 46.486 0.9100 0.4900  
3255 QQSWQ3_3_1(N) 3000.0pF 30.00pF 2 C 462 437 0 Ignore 21.00pF 0.61pF 0.0008 83.052 46.486 0.9100 0.4900  

QSQ1
Device Loc Side Total Pin Tested Coverage (%) Comment
QSQ1 B4 T 3 3 100.0  

Pin Nail Net Name
1 399 N18147149
2 1590 S_SMBCLK_MAIN
3 327 S_SMBCLK_VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3260 QSQ1_1_2 3000.0pF 3000.0pF 1 C 399 1590 0 Ignore 2100.0pF 4184.5pF 5.8055 51.675 16.336 3900.0 2100.0  
3261 QSQ1_2_3_1(N) 5.000V 0.700V 4 Q 1590 327 339 0.910V Ignore 0.690V 0.0003 207.63 199.64 0.9100 0.4900  
3262 QSQ1_3_1 0.700V 0.700V 0 Q 1590 327 0 0.910V 0.490V 0.660V 0.0000 16728486 13472334 0.9100 0.4900  
3263 QSQ1_3_1 3000.0pF 30.00pF 2 C 399 327 0 Ignore 21.00pF 0.66pF 0.0000 16728486 13472334 0.9100 0.4900  

QSQ19
Device Loc Side Total Pin Tested Coverage (%) Comment
QSQ19 D2 T 3 3 100.0  

Pin Nail Net Name
1 1195 N28268489
2 1 GND
3 1337 P_VCORE_VRHOT__R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3256 QSQ19_1_2 3000.0pF 100.00pF 2 C 1195 1 0 Ignore 70.00pF 100.93pF 2.2900 4.3670 4.2320 130.00 70.000  
3257 QSQ19_2_3_1(N 5.000V 0.700V 4 Q 1 1337 1195 0.910V Ignore 0.030V 0.0002 415.26 909.57 0.9100 0.4900  
3258 QSQ19_3_1 0.700V 0.700V 0 Q 1 1337 0 0.910V 0.490V 0.580V 0.0000 8026552 3506909 0.9100 0.4900  
3259 QSQ19_3_1 3000.0pF 30.00pF 2 C 1195 1337 0 Ignore 21.00pF 0.58pF 0.0000 8026552 3506909 0.9100 0.4900  

QSQ2
Device Loc Side Total Pin Tested Coverage (%) Comment
QSQ2 A4 T 3 3 100.0  

Pin Nail Net Name
1 399 N18147149
2 1591 S_SMBDATA_MAIN
3 328 S_SMBDATA_VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3267 QSQ2_1_2 3000.0pF 30.00pF 2 C 399 1591 0 Ignore 21.00pF 23.44pF 0.5471 5.4840 1.4860 39.000 21.000  
3268 QSQ2_2_3_1(N) 5.000V 0.700V 4 Q 1591 328 399 0.910V Ignore 0.430V 0.0004 156.95 41.698 0.9100 0.4900  
3269 QSQ2_3_1 0.700V 0.700V 0 Q 1591 328 0 0.910V 0.490V 0.660V 0.0008 83.052 65.346 0.9100 0.4900  
3270 QSQ2_3_1 3000.0pF 30.00pF 2 C 399 328 0 Ignore 21.00pF 0.66pF 0.0008 83.052 65.346 0.9100 0.4900  

QSQ21
Device Loc Side Total Pin Tested Coverage (%) Comment
QSQ21 D2 T 3 3 100.0  

Pin Nail Net Name
1 1196 N28268491
2 1 GND
3 1195 N28268489

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3264 QSQ21_1_2 0.700V 0.700V 0 Q 1196 1 0 0.910V 0.490V 0.790V 0.0000 11537800 6805577 0.9100 0.4900  
3265 QSQ21_2_3 1.500V 0.300V 4 Q 1195 1 1196 0.390V Ignore 0.130V 0.0000 91830264 83637792 0.3900 0.2100  
3266 QSQ21_3_1 0.700V 0.700V 0 Q 1196 1195 0 0.910V 0.490V 0.780V 0.0000 5883753 3634142 0.9100 0.4900  

QSQ46
Device Loc Side Total Pin Tested Coverage (%) Comment
QSQ46 B4 T 3 3 100.0  

Pin Nail Net Name
1 440 N18996429
2 456 S_SATALED__R
3 225 HDLED-

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3286 QSQ46_1_2 0.700V 0.700V 0 Q 440 456 0 0.910V 0.490V 0.790V 0.0000 4838469 2719431 0.9100 0.4900  
3287 QSQ46_2_3 1.500V 0.300V 4 Q 225 456 440 0.390V Ignore 0.150V 0.0002 177.97 109.75 0.3900 0.2100  
3288 QSQ46_3_1 0.700V 0.700V 0 Q 440 225 0 0.910V 0.490V 0.590V 0.1657 0.4230 0.2050 0.9100 0.4900  

QSQ6
Device Loc Side Total Pin Tested Coverage (%) Comment
QSQ6 A4 T 3 3 100.0  

Pin Nail Net Name
1 373 P_VR_READY_10
2 346 N97614572
3 347 N35715912

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3310 QSQ6_1_2 3000.0pF 3000.0pF 2 C 373 346 0 Ignore 2100.0pF 4575.9pF 14.774 20.305 15.249 3900.0 2100.0  
3311 QSQ6_2_3_1(N) 5.000V 0.700V 4 Q 346 347 373 0.910V Ignore 0.520V 0.0010 69.210 8.2990 0.9100 0.4900  
3312 QSQ6_3_1 0.700V 0.700V 0 Q 346 347 0 0.910V 0.490V 0.600V 0.0008 83.052 43.600 0.9100 0.4900  
3313 QSQ6_3_1 3000.0pF 30.00pF 2 C 373 347 0 Ignore 21.00pF 0.60pF 0.0008 83.052 43.600 0.9100 0.4900  

QSQ9
Device Loc Side Total Pin Tested Coverage (%) Comment
QSQ9 A4 T 3 3 100.0  

Pin Nail Net Name
1 347 N35715912
2 1 GND
3 871 S_VCCST_PWRGD

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3317 QSQ9_1_2 3000.0pF 100.00pF 2 C 347 1 0 Ignore 70.00pF 109.46pF 3.3707 2.9670 2.0320 130.00 70.000  
3318 QSQ9_2_3_1(N) 5.000V 0.300V 4 Q 1 871 347 0.390V Ignore 0.040V 0.0000 61410008 114900968 0.3900 0.2100  
3319 QSQ9_3_1 0.700V 0.700V 0 Q 1 871 0 0.910V 0.490V 0.580V 0.0000 11142745 4945876 0.9100 0.4900  
3320 QSQ9_3_1 3000.0pF 100.00pF 2 C 347 871 0 Ignore 70.00pF 0.58pF 0.0000 11142745 4945876 0.9100 0.4900  

QUQ706
Device Loc Side Total Pin Tested Coverage (%) Comment
QUQ706 A2 T 3 3 100.0  

Pin Nail Net Name
1 1489 P_5V_USB_GATE_10
2 1229 +5VSB_DUAL
3 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3391 QUQ706_1_2 3000.0pF 4000.0pF 2 C 1489 1229 0 Ignore 2800.0pF 3915.4pF 39.560 10.111 9.3980 5200.0 2800.0  
3392 QUQ706_2_3_1 5.000V 0.300V 4 Q 1229 3 1489 0.390V Ignore 0.000V 0.0000 732826880 1682589440 0.3900 0.2100  
3393 QUQ706_3_1(N) 0.700V 0.700V 1 Q 3 1229 0 0.910V 0.490V 0.630V 0.0008 83.052 56.686 0.9100 0.4900  
3394 QUQ706_3_1(N) 3000.0pF 4000.0pF 2 C 1489 3 0 Ignore 2800.0pF 0.6pF 0.0008 83.052 56.686 0.9100 0.4900  

QUQ730
Device Loc Side Total Pin Tested Coverage (%) Comment
QUQ730 A4 T 3 3 100.0  

Pin Nail Net Name
1 379 P_USBPWR_SW
2 1 GND
3 971 P_5V_USB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3395 QUQ730_1_2 3000.0pF 100.00pF 2 C 379 1 0 Ignore 70.00pF 90.64pF 2.1051 4.7500 3.2690 130.00 70.000  
3396 QUQ730_2_3_1 5.000V 0.300V 4 Q 1 971 379 0.390V Ignore 0.030V 0.0002 177.97 358.58 0.3900 0.2100  
3397 QUQ730_3_1(N) 0.700V 0.700V 1 Q 1 971 0 0.910V 0.490V 0.690V 0.0000 10716933 10120928 0.9100 0.4900  
3398 QUQ730_3_1(N) 3000.0pF 200.00pF 1 C 379 971 0 Ignore 140.00pF 0.69pF 0.0000 10716933 10120928 0.9100 0.4900  

QUQ731
Device Loc Side Total Pin Tested Coverage (%) Comment
QUQ731 A4 T 3 3 100.0  

Pin Nail Net Name
1 378 USBPWR_SW_
2 1 GND
3 971 P_5V_USB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
3399 QUQ731_1_2 3000.0pF 100.00pF 2 C 378 1 0 Ignore 70.00pF 117.79pF 2.2228 4.4990 1.8300 130.00 70.000  
3400 QUQ731_2_3_1 5.000V 0.300V 4 Q 1 971 378 0.390V Ignore 0.030V 0.0002 177.97 351.85 0.3900 0.2100  
3401 QUQ731_3_1(N) 0.700V 0.700V 1 Q 1 971 0 0.910V 0.490V 0.690V 0.0000 5340682 5006542 0.9100 0.4900  
3402 QUQ731_3_1(N) 3000.0pF 200.00pF 1 C 378 971 0 Ignore 140.00pF 0.69pF 0.0000 5340682 5006542 0.9100 0.4900